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Yes, I've checked the DC operating point and every mosfet is in saturation. I biased the input transistors using large drain-to-gate feedback resistors, in this case implemented using pseudo pmos resistors. This is the schematic of the op-amp. but I don't think the problem is here. It's a simple...
Yes, I followed this procedure, and the V(out)/V(8) vs. frequency print was the following:
https://obrazki.elektroda.pl/5436736700_1472583090.png
For me, it still doesn't make any sense or my interpretation of the graph is flawed. Taking into account the AC response of V(out)/V(7) and the tran...
I'm sorry because it seems I'm completely missing the point. Are you talking about replacing the iprobe with an ac voltage source and using that as the probe for my stb simulation? I've done so and set the AC magnitude of this ac voltage source to 1V. However, it seems the loop gain (magnitude...
The problem is that there isn't a voltage probe in analoglib, only the iprobe, that's why I assumed it was the only option.
Very grateful for your help by the way.
In order to simulate the loop gain I simply placed the iprobe in a location that opens up the loop (as shown in the schematic) and did a stability analysis from 0.1Hz to 1GHz. After that, I plotted the loop gain (magnitude and phase). I'm really inexperienced when it comes to designing...
Hi! Everything you said makes sense and I undestand how it works now. But do you have any idea why the loop gain (A*Beta) that I've obtained is negative (in dB)? This mean the loop gain has crossed 0dbs close to DC so the system is unstable?
Thanks for everything!
Hi. C9 and C10 actually represent the neural electrode model while the other capacitors are used to implement an high pass filter.
To simulate the loop gain I just placed the probe in a location that opens up the loop. This was the first time I've simulated the loop gain, am I missing something...
C9 and C10 capacitors are needed to represent the model of the neural electrode. C19,C20,C21,C22 are used to implement an high pass filter because I wish to cut out DC. I have some DC offset on the input inside the opamp itself. Thanks!
Hi everyone,
This is the first time I'm designing a differential amplifier on Cadence (an amplifier for a neural probe) and after doing a stability analysis something strange happened: The loop gain doesn't correspond to the gain I obtained when doing an AC analysis (the one I desired) and I...
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