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Recent content by ads-ee

  1. ads-ee

    vhdl signal generator

    The description just mentions what happens to the output DOWN if the input GO goes high. The description is poorly worded, but clearly defines the behavior. Here is a summary of the description, that might make more sense. The outputs UP and DOWN respond to the input GO as follows: If GO...
  2. ads-ee

    Skew constraints on asynchronous signals

    @mtwieg you should probably consider specifying placement constraints for the input/output/gating logic for these "gated" signals. Co-located input/output for each of the signals, replicate the same relative placement on another set of pins, use information from the FPGA manufacturer on the...
  3. ads-ee

    How to constrain a source-synchronous FPGA input?

    I'm not sure you are specifying your FPGA input constraints correctly you seem to be applying the external chip setup and hold values to your FPGA inputs. The output delays of the external chip along with the skew between the output clock.data and the trace delays should be used to generate...
  4. ads-ee

    Running Modelsim commands on Linux that is installed on Windows PC.

    WSL is a barebones virtual machine running Linux. You can't run Windows programs using the Linux kernel, the programs have to be compiled to run on Linux itself. If you want to take advantage of the shell scripting of Linux then install the Linux version of Modelsim on WSL.
  5. ads-ee

    FLASHPRO JTAG signal integrity

    TMS should never float that is the signal that moves a TAP controller through the FSM. Do you have the TMS line connected to a pullup?
  6. ads-ee

    Shift register error

    Well maybe it's not illegal, but it also looks like they are implementing a gated clock in an FPGA which is inadvisable.
  7. ads-ee

    Synopsys PrimeTime/TestMax and Xilinx Vivado

    AFAIK, Vivado doesn't output .db files. Vivado also does it's own timing analysis during and after place and route. Not exactly sure why you are trying to use ASIC tools on an FPGA.
  8. ads-ee

    Shift register error

    I would wager they used inout because they had a problem with Q can't be read (when it was defined as an out). Most posters new to VHDL don't set their tools to compile to the 2008 standard. If you use the older VHDL standard when you change Q to an out you can't read Q (Q on the right hand...
  9. ads-ee

    Differential outputs on Arty-A7

    What drives buff_in? You don't show how that is produced, if it never toggles the output of the ODDR will never change. The C input needs both rising and falling edges to output the D1 and D2 inputs.
  10. ads-ee

    Implementation of AXI UART16550 with RS-422

    The "engineering" comes with reading the documentation and understanding what each component does and how it works. https://www.xilinx.com/support/documentation/ip_documentation/axi_uart16550/v2_0/pg143-axi-uart16550.pdf The BRG (Baud Rate Generator) is describe in the IP documentation.
  11. ads-ee

    Post-Synthesis simulation problem

    In the 30+ years I've been working on FPGAs I've only had to resort to post synthesis simulation twice. Once was to verify the synthesis results were not the same as the design description. The synthesis tool had a bug and we had to migrate to a different version of the tools. The second time...
  12. ads-ee

    Is bluetooth earbuds permanently damaged or it possible to repair?

    Splash resistant doesn't mean wash resistant. When they say something is splash resistant it's for things like getting slightly wet from rain drops (not a heavy downpour or sticking it under a sink faucet). Even considering the idea of washing the the case and earbuds was a mistake. If you are...
  13. ads-ee

    Understanding Microarchitecture of legacy IPs

    I found this after a couple of minutes of going through various links using a search on "68000,68010,68020". https://archive.org/stream/68000_68010_68020_Primer/68000_68010_68020_Primer_djvu.txt You need to learn how to effectively use a search engine and parse the results. This link didn't...
  14. ads-ee

    Is there any open source MCU Verilog HDL code implemented with RISC-V?

    https://opencores.org/projects?expanded=Processor There are 5 of them listed on open cores. Don't know if any of them are worth looking at.
  15. ads-ee

    How to modify delay cycles to enable reading in fifo generator?

    Won't improve the situation unless you use a synchronous FIFO, then you run into the problem where you can't supply two different clocks (that may be synchronous but at different frequencies) to that FIFO. Back in post #2 I already suggested the best way to deal with the two different clocks if...

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