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Yes, you understand correctly the problem.
In the meantime, I solved the issue with my original idea:
output <= registers(to_integer(address)) when not Is_X(address) else (others => 'U');
I checked results generated by the synthesis tool, and it seems that it properly ignores (set False)...
Sorry, I don't get your point.
What do you mean by normal assignment of the "output" vector?
The code:
output <= registers(to_integer(address))
will synthesise to a valid implementation.
As you see, I want to have a fully combinatorial logic (multiplexer). The address is a combinatorial...
I am assigning don't care values in order to give more room for a synthesis tool. As an example, if you have data accompanied by a valid strobe, forcing them eg. to 0 when the strobe is not active, may not be the best from logic utilization point of view. You still need to assign something in...
Hi,
I have an array of std_logic_vectors. The address selector (unsigned type) may intentionally be unsigned to don't care/unknown state in order to simplify logic in other parts of a design. In such a case, the simulator will generate a warning, however, the output vector will be assigned to...
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