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Thank you everyone! Finally, I was able to complete the total flow. It is not pretty I must say!
If anyone needs help, I will be more than happy to help!
Thanks again.
Thank you, everyone!
I just have one issue left. When I import the GDSII file (generated by IC Compiler) into Custom Compiler and run LVS, I see that pin labels are not preserved. When I put the pin labels it passes the LVS and everything checks out fine. But, I want to avoid this manual pin...
Thank you @ThisIsNotSam and @oratie. Eventually, I found a way to resolve the issues mentioned above. Now, I'm struggling with the issue in the case of simulating the schematic. After I imported the schematic using veriliog import-in, I have a symbol view and schematic view of the circuit(...
Hello ThisIsNotSam, Thanks for your reply.
Can you please elaborate on the merging on the environment that you mentioned?
And, secondly, I'm using the custom compiler to import the GDSII file generated in the IC compiler (I'm trying only synopsis flow this time). There's an option where it...
Hello Everyone,
I have a P&R layout that I have created using IC compiler with the SAED EDK90nm design kit. Then I made a GDSII file from it and tried to import it both in cadence virtuoso and synopsys custom designer. First, I have created a library and attached it to the technology library...
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