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Hi everyone,
Is there a way to connect multiple drivers to a single port in FPGA synthesis. Here is a sample code:
...
signal out: std_logic_vector (7 downto 0);
signal in1: std_logic_vector (7 downto 0);
signal in2: std_logic_vector (7 downto 0);
signal in3: std_logic_vector (7 downto 0)...
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