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Recent content by Adam2008

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    Need help for career in vhdl/fpga design

    Hi guys, I am in analog design track. However I really had a difficult time to find a job without experience. I am thinking of switching to fpga/vhdl design. Is it possible to find a job after taking some courses in this area? And what courses(or training program) shall I take? Thanks a...
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    Error when importing GDS file using Cadence

    Dear all, When I tried to import a GDS file from CIW, File-->import-->Stream, there are some errors: Anybody know the reason? Thanks in advance, Adam \o Added CIW menu. \w *WARNING* No user triggers registered for viewType schematic. \w *WARNING* No user triggers registered for viewType...
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    Error when importing GDS file in Cadence

    Dear all, When I tried to import a GDS file from CIW, File-->import-->Stream, there are some errors: Anybody know the reason? Thanks in advance, Adam \o Added CIW menu. \w *WARNING* No user triggers registered for viewType schematic. \w *WARNING* No user triggers registered for viewType...
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    Assura DRC error: Ratio >= 0.0004

    Latch up problem Hi, Dear Friends, Assura DRC shows some error like this: Ratio (RX TripleWell contact)/(NFET gate not over N3) >= 0.004. This is an error related to Latch up. There are already guard ring added to the active components. What are some other method which will...
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    Some error of layout presented by Assura

    Hi Friends, I got some error when doing DRC using Assura: Rule No. 815 : GRLUP09b: Ratio (RX substrate contact)/(NFET gate not over N3) >= 0.007. I am not sure what this message means. Would you please give me some hint? Thanks, Adam
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    Assura can not be started

    vuidrcrun Dear Friends, I am using assura DRC and LVS. However, Assura can not be started. The error message in CIW is: ibmPdkRunAssuraDRC() *Error* eval: undefined function - vuiDRCRun <<< Stack Trace >>> (... in ibmPdkRunAssuraDRC ...) ibmPdkRunAssuraDRC() ERROR The version...
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    Question of drawing layout in Virtuoso

    I got it. Thanks again. Adam
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    Question of drawing layout in Virtuoso

    Hi, prashantbabu, It works. Thanks a lot. Would you please also let me know what is "Gravity" for? Adam
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    Question of drawing layout in Virtuoso

    Hi Friends, I got some question on drawing the layout in virtuoso: 1. The size of rectangulars(metals) can not be controlled as expected. Usually it will just match the size as the rectangulars already exist there, or it will match the corners of some rectangular. This is very weird...
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    DRC question in Virtuoso

    In the layout window, I choose verify->DRC, there is a form popped out. What shall I fill as the "rules file" and "rule library". The defaut value are invalid. Is the rule library same as the technology library? Thanks. Adam
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    Layout in Cadence Virtuoso

    Thanks a lot. Adam
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    Layout in Cadence Virtuoso

    Hi friends, I am new to Virtuoso layout. Would you please recommend some tutorial I can read to learn the procedure(from the beginning to ready to submit) of doing layout some analog circuit? Thanks a lot. Adam
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    Questions about pcell using cadence virtuoso

    pcell，symbol Hi Paramjyothi, Thanks for your help. Where can I find the propety of the pcell? Thanks again. Adam Added after 3 minutes: Hi k_90, I have tried what you suggested, not work. That's why I post it here. Adam
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    Questions about pcell using cadence virtuoso

    edit pcell cadence Hi, I am using cadence virtuoso to design a VCO. When generate layout from my schmatic, I am not able to see the pcell of the components. THere are only symbols with names in the layout window. How can I see the pcell of the components? Thanks.
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    How to realize the voltage reference?

    Thanks. Could you give more detail about the bias current generator?
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