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Recent content by Actel_FAE

  1. A

    Output Delay Problem For 32 bit output (+ 50 points for sol)

    xilinx & output delay What do you plan to do with the design ? .. Have you tried downloading the program onto the board and checking for operation ? ... Try using the gloal resources ....the low skew lines !!!
  2. A

    FPGA selection criteria

    criteria to select fpga These are the general criteria for FPGA selection . -- Capacity (Gatecount) -- Power Consumption (for handheld / low power projects refer to www.actel.com) -- IO's (User IO's) -- IDE .. Free or Paid software ? -- Cost of device -- Flash or Antifuse Devices (ACTEL...
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