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Hello all,
our company designs and manufactures industrial display systems:
andon for production monitoring, displays for photovoltaic systems,
timers, counters, variable message panels, process displays and more.
We have process displays with 4-20mA input as well as alphanumeric
ModBus...
hand soldering mlp
You absolutely require an air soldering station.
Anyway, you can hand solder these devices only
for prototypes.
Someone has done this job with a small kitchen
oven used as a convection oven. I don't remember
the web link but you can try to use google to find it.
Regarding...
soldering mlp
I did. It's a very difficult task but it's possible: you'll need an air soldering station and a lot of patience. X-Ray is not necessary because you can visually inspect the soldering. Remember to put as little solder paste as possible.
A.C.
Re: OLed panels/displays
Very interesting, but the price is higher than
what you said:
for $19.95 you get the bare carrier board.
The OLED display costs $34.95.
Regards,
A.C.
Re: LVDS Signalling
I've used standard 100 ohm resistors as
terminators.
Now I'm trying with a multidrop configuration
and I'm having better results.
Maybe it was an issue due to saturation of the
LVDS differential inputs of the PLL. Having
a multidrop configuration or a total impedance
that...
Re: LVDS Signalling
Dear YUV,
my clock frequency is 45MHz -> 22ns period.
I think a 22ns period can tolerate a 0.5ns jitter.
This 0.5ns interval should be not accumulated
since each board re-generates clock signal.
Infact, the output clock is generated by a state
machine and it is treated...
Re: LVDS Signalling
Dear Kib,
I really cannot understand why this clock jitter
appears only at the n-th board if n is greater
than ten. My system is designed so that each
board receives clock and data and then regenerates
new clock and data signals synchronously.
There should be no jitter at...
Re: LVDS Signalling
I know for sure that the PLL loses its lock since I'm using
the 'locked' output of the PLL megafunction in the FPGA. Each
time PLL loses its lock I force it to re-lock and I can see this
happening from the outputs of each board.
Yes, I'm using the x2 clock for internal...
Re: LVDS Signalling
This is how data and clock looks like. You can see that data lines transitions are synchronous to clock in order to minimize noise. So I need a 180deg. delayed, 2x clock inside the FPGA to read data lines.
Hope this helps to figure my system.
So you say that you have a...
Re: LVDS Signalling
The PLLs are integrated in the FPGAs in each board.
Each board has got one FPGA. Each FPGA has a PLL
that locks on the incoming LVDS clock signal (~20MHz)
and reads the serial LVDS data. A new clock signal
(in-phase with that data) is retransmitted to the next-in-chain
board.
Re: LVDS Signalling
No, clock is not extracted from data. A differential pair is used to
transmit clock from one board to the next in chain while 5 other pairs
are used just for data and sync. So, data coding is not crucial.
What happens is a PLL loss of lock when the total number of boards
in...
Re: LVDS Signalling
I'm not using a multidrop configuration but multiple
point-to-point connections. Each board has an RX
section and a TX section that retransmits the same
data received.[/img]
Re: LVDS Signalling
I'm using LVDS for communication between FPGAs on different boards.
I'm experiencing loss of lock problems on the PLLs when I get 10 or more FPGAs in chain.
Any help?
Re: LVDS Signalling
Another question for you:
in point to point, board to board, LVDS communications, has
anyone experience in placing series resistors on ground
signals in order to minimize ground bounce?
Such a solution is used in RS485 connections.
Let me know.
A.C.
Dear friends,
I need your help for an LVDS question.
According to your direct experience,
how important is impedance matching
in VHDL signalling at 150Mbps and for
a 1m distance point to point communication?
How much the eye pattern will close
if I don't respect the 100 Ohm differential...
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