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Recent content by acbelgad

  1. A

    NOR linear FLASH IP CORE for xilinx

    I want to use NOR linear flash (Intel JS28F256P30T95) present on xilinx ML507 kit to write and readback data. Can someone send me link to free ipcore for the same or any other helpful document to start with.
  2. A

    DDR2 implementation using xilinx IP core

    Thanks for replying...i have checked everything and its correct...DDR2 top needs two clocks : sys_clk and idly_clk_200. What is the best way to give these clocks from xilinx ML507 board. This board has 33MHz and 27MHz oscillators.
  3. A

    DDR2 implementation using xilinx IP core

    I generated DDR2 Xilinx IP core. In IP core directory, there are two design folders : example design and user design. What is the difference between two. I used example design as it is unchanged and flashed on ML507 kit but phy_init_done and cal_done signals are not getting high on chipscope...
  4. A

    [SOLVED] ROM implementation on FPGA

    I used single port ROM ip core in my vhdl code. How to write ROM with initial values.
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