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Thank you erikl, it is really a good news for me. I'll leave this problem alone, and go to tapeout.
when the testing results come out, I'll post some results.
Dear guys,
Due to the periodic drift of the output CM level, the outputs (Voutp & Voutn) of a fully differential amplifier accordingly drift even with sufficient SR and UGB, as shown in the figure attached. This is the typical case.
However, if we look at the differential signal...
dear dick,
I have no idea of what the "gate" between the serpentine folds actually is.
It seems this structure only increases the parasitic MOS/Cap just as ajay said.
Dear all,
Recently, I've found a type of MOS Transistor characterized by snake-shape layout (pls refer to the figure attached),
NMOS
one prominent advantage of this type of transistor is it makes the layout quite compact for very large ratio of L/W.
I just wonder, whether it has other...
Dear erikl,
According to you suggestion, AVSS & DVSS are finally shorted at the top level. However, it is not what I expected.
AVSS & DVSS are typically separated at the PAD Ring, thus the PAD Ring is typically divided into several sections (i.e. through cellcut), each has individual Power...
Dear all,
I'm doing the layout for a mixed-signal system on the P-SUB CMOS Process these days, there're two grounds AVSS & DVSS for Analog domain and Digital Domian.
Both Analog Core and Digital Core are enclosured by two dedicated Nwell Guarding Rings separetely, thus the Calibre LVS for...
Not the reason.
I suppose it is due to some facts which are out of our normal scope of view.
PS: These days it is again out of work:)
What a weird problem!
It is amazing when I find the "shift+select" function has been recovered automatically.
It is really weird.
Many Thanks to electronics_rama & vijaya.kumar for your suggestions.
Still open for explaination:)
Dear all,
Recently, I've found that I cannot do a simultaneous selection in Virtuoso Layout.
For example,
I cannot select the two metal traces (A & B) at the same time.
I'm highly suspicious of the Option Setting, which has not been properly set.
BTW, my Virtuoso Virsion is IC615
Can...
Hi Guys.
Recently, I'm getting interested in the PRN Generator Using Linear Feedback Shifting Register(LFSR).
If Low Power Performance is desired, which Logic Type and clock strategy are preferred.
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