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hi all, can anyone please help me to delay the time? the input reads too fast.
library ieee;
use ieee.std_logic_1164.all;
entity test1 is
port( clk:in std_logic;
input:in std_logic;
output:out std_logic_vector(6 downto 0));
end entity test1;
architecture behavior of test1 is...
shift register
thanks for helping..may i know how do i connect when i wan to download to UP2 board for testing?both the inputs and outputs... may i know wat is cnt8 and temp for?wat is one_b_fs,Fclk and Tclk? can simply explain how the thing works?i found some error during the "signal...
hi all...i am trying on codes for shift register...does anyone can help me to write a test codes so that i can try them out? pls guide too where to input n output the pins on UP2 board using CPLD..thanks!
library ieee;
use ieee.std_logic_1164.all;
entity shift_register4 is
port(reset: in...
pretty thanks for u all!! really appreciate for helping..!!^.^
now i am trying in some codes but faced some problem during compilation..does any of u willing to help me?
hello all,
i am newbie here and i am currently working on an assignment.
for this assignment, i need to take in 10 bytes of data serially from RD232 into FPGA using VHDL codes and then display out on the 7-segment using MAX chip.besides, they can stored in SRAM.
i got no idea at all on how to...
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