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Re: how we remove these off grid errors in 45 nm Technology
Hi there,
How to avoid
A.Off-grid errors
B.Off grid shap errors:
1. Off grid polygon on layer Metal1
2. Off grid poly gon on layer poly.
thanks in advance!
hello sir,
thanks for the reply but sir it has also 90 nm technology 's drc file. but my need is DRC file of 45nm. i have also attached by CIW Window process( CIW Window>>Technology File manager>>Attach ). but during drc run time i shows option only undefined and 90nm . plrase tell me another...
ERRORS
1.Poly area must be o.1 µm.
In this problem how did i incease poly area and please tell me how did it adjust.
2.Nwell width must be 0.6 µm.
please explain it and please tell me how did it adjust.
3.Pimp to gate end enclosure must be 0.18µm.
please explain it and please tell me sir with...
hello sir,
Hi, I am trying to run DRC but in technology option it's not showing my library i.e. cmos45 nm. even I have attached in startup of schematic and schematic is running fine but for layout DRC is not running. It shows in DRC as undefined. no option is there of designated library cmos...
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