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Hi am using synopsys design compiler for synthesizing my design and using the netlist in VCS simulation and am getting warning as,suppose i use a reg[10:0] and am assigning to a signal B[5:0] during synthesis the remaining bits are considering as dontcares by the synthesys tool and functionality...
HI am using SRAM 28nmHPC lib(.v) in my design and intantiating it to my design it gives warning as
"input a unknown/high-Z in read cycle at simulation time 11.0"
how can i reslove this issue am using XIlinx ise and simulating it,the design works fine when am using user ram.
can any one...
how to use spi interface with custom ip
Hi I have a custom ip with GPIO port and i have to interface this gpio with SPI interface,means which ever data is in flash is to be sent to custom ip through spi interface,the whole system is to be build on zc702 how this can be done can anyone help me...
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