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Recent content by abhii

  1. A

    Looking for tutorials for simulation, synthesis, layout in Alliance CAD

    I don't think you can use verilog with alliance cad tools. You can use some other verilog simulation software like icarus verilog simulator which is free. If you do get a good tutorial for alliance cad tools please do let me know as well[COLOR="Silver"]
  2. A

    Calibre DRC/LVS student guide and lab

    Thanks a lot for the material
  3. A

    help needed with parametric analysis in spice

    I am using PSpice student version
  4. A

    help needed with parametric analysis in spice

    well how do i do that?and besides doesn't the statement .param l_val specify that l_val is a global which will be varied?
  5. A

    help needed with parametric analysis in spice

    i need to do a parametric analysis in spice to show the different drain current curves with varying channel length of NMOS. But i am getting an error can anyone plz help me out vds 1 0 5v vgs 2 0 m1 1 2 0 0 n1 .param l_val = .1u .model n1 nmos level = 2 tox = 50n nsub = 1e16 l = l_val w = 10u...
  6. A

    how to generate prbs in cadence

    prbs in cadence Hi, How do i generate a prbs sequence in cadence?
  7. A

    circuit methods to solve signal integrity issues in DSM

    Hi, Can anyone suggest some methods to solve signal integrity problems in DSM technologies.
  8. A

    what happens to speed as gain increases?

    Hi, I wanted to know what happens to the speed of a digital circuit when the gain is increased. do we have to sacrifice noise margin for speed?
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