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Hello, I have a problem when simulating an inverter created with smic 65nm technology library.
Here is a screenshot for the error messages
Also I don't know what model files to choose, Is it .ckt files or .mdl files
and in the simulator_version.txt file it mentions that it should be...
the error says that cadence fails to load FreePDK45.tf
it shows a lot of errors on the CIW
should I change the hole tech library ?
If yes, Is there another one that I can download ?
Thanks
I have some problems with the NCSU_TechLib_FreePDK45:
- I looked for the file divaDRC.rul for the DRC but I did not find it.
- cadence is not able to integrate the FreePDK45.tf technology file.it shows me an error that it fails to load it.
I think this is the cause of the problem that prohibits...
when I type the comand ./install after copying the install.ixl folder to /opt/mentor , it gives me this error:
*** Warning with: ./install
The version of /usr/bin/java may not be correct!
...Required: "1.6.0"
...Found: java version "1.7.0_181"
OpenJDK Runtime Environment...
conserning the PDK, the TechLib file contains just layouts ,and schematics are in the NCSU_Devices_FreePDK45 folder, this might be the problem, so I copied the schematics to each cell in the TechLib.
conserning the skill function I get errors in WIC (photo)
for the primitive layout I think It...
I encountered this problem when I tried to generate layout from schematics automaticaly.
after doing connctivity > update > binding I got this result
Please help me to solve the problem.Your help appreciated
I don't have assura in toolbar.Des that mean that it is not enabled? that's why I tried to use Verify > DRC , when I have copied calibreDRC.rul to my tech folder(NCSU_TechLib_FreePDK45, I see an error in the WIC:
how can I solve the problem?
Your help appreciated
When I try to zoom in order to see the layers of the device ,I tried to increase stop in options > display but it shows me a " X " fill. I tried to change properties, but I don't know exactly the properties to add, chould I modify cell properties or instance properties.
Also ,I have a warning...
Re: Layout problem when trying to see layers
I have a warning in WIC of cadence when adding a pmos_vtl to my layout, it says that :
The Pcell super master: NCSU_TechLib_FreePDK45/pmos_vtl/layout is not a SKILL super master.
The usage of non-SKILL Pcells in Virtuoso is not a supported feature...
Re: Layout problem when trying to see layers
I tried to do what you have said, but I don't know exactly the properties to add, chould I modify cell properties or instance properties. Thank you for your help.
Layout problem when trying to see layers
When I try to zoom in order to see the layers of the device ,I tried to increase stop in options > display but it shows me a box with a cross on it.your help appreciated
when I try to start cadence virtuoso 6.17 with the command : virtuoso &
an error message shows up:
No protocol specified
*WARNING* X Window Display Initialization failure
*WARNING* (DISPLAY ":0.0")
Can you help me please with this.Thank you
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