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Recent content by abc_81

  1. A

    information needed on fault collapsing

    Hi, If there is any good documentation on fault collapsing, please share it . Thanks Vijayalakshmi
  2. A

    difference between ATPG library and verilog library

    Hi, Whats is the difference between libraried that we use for ATPG and verilog library ? Thanks
  3. A

    Hold Violation in Tester and regeneration of ATPG with hold mask

    Re: ASIC-DFT Hold Violation in Tester and regeneration of ATPG with hold mask How to identify the failing flop during chain test failure on silicon ?
  4. A

    How to debug failing chain pattern ?

    If the chain pattern is failing on silicon, how to identify the failing flop ?
  5. A

    DFT scan insertion querry

    to be specific, I wanted to know if we can use lockup latch between pos edge flop and neg edge flop in a single scan chain or lockup latch should be used only between different clock domain ?
  6. A

    DFT : querry on compression

    We are using testkompress tool for compression. If I use this tool and if I know the area(flop count), how do I calculate the compression ratio ?
  7. A

    DFT - chian pattern failure

    I have used serial testbench for the chain pattern. With this simulation is failing. To debug this I have run parallel simulation with post_shift to idendify the failing flop. Is it the right approach ?
  8. A

    DFT - chian pattern failure

    Thanks for the response. Simulation is actually failing , so I have run pareallel simulation with post_shift=5 option in mgc tool.
  9. A

    DFT : querry on compression

    Hi , How to decide compression ratio ? what is the limitation on compression ? will it affect coverage ? Is there any generic architecture for compression ? please provide good document on scan compression
  10. A

    DFT scan insertion querry

    Hi , I am working on scan insertion. I have some querries on the same. My understanding is lockup latch is not needed when we have negedge flop followed by pos edge flop. But when we have pos edge flop followed by neg edge flop, can I use lockup latch between pos edge -> lockup latch -> neg...
  11. A

    DFT - chian pattern failure

    Hi, Please help me in understanding the following, How to debug chain test failure ? How to find the failure flop for chain test patterns? What is the pattern used for chain test ? is it specific to the tool or can it be same for all ? Thanks Viayalakshmi
  12. A

    clock latency & uncertainity

    Thanks for answering my querry. Can you please explain me more on clock uncertainity ? Thanks
  13. A

    clock latency & uncertainity

    Hi, What is clock uncertainity ? How is it different from clock latency ? How library specific clk gating cells can avoid glitches as compared to using a simple AND gate for clk gating ? Thanks
  14. A

    what does it mean "deterministic ATPG "?

    determinic ATPG Hi, Please let me know what is deterministic ATPG ? Thanks
  15. A

    compression technique -LBIST

    Hi, What is LFSR ? why it is specifically used in LBIST ? Thanks

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