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Recent content by Aastik

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    Latest Version of QuestaSim?

    questasim Hi, Now version 6.3f is available. Regards.
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    Latest Version of QuestaSim?

    questasim latest version Hi, What's the latest version of Mentor's QuestaSim available? Regards.
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    Xilinx ISE Timing constraints

    Hi Nag123, after seeing your design block diagram, i suggest following points: 1. your input clock to the FPGA is 45Mhz, then you need to give PERIOD constraint to this clock only i.e. 45 mhz. 2. since your DCM is generating 90Mhz, it will automatically put constraint on 90Mhz and report the...
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    help me with a concept of using FPGA to verify ASIC Design

    Re: help me with a concept of using FPGA to verify ASIC Desi Hi, Verifying the SOC Rtl using FPGA is very fast as compared to simulation. And it gives more test coverage also. Some simulation can take days to complete whereas it can be done in FPGA in minutes. In this particular case, I...
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    RGMII (Ethernet) on FPGA?

    rgmii fpga Hi, I want to know if anybody has successfully implemented RGMII (Reduced Gigabit MII) interface on FPGA. RGMII uses DDR (Double data rate) at 125Mhz. What I think is that it may not be straightforward to get FPGA working at 125Mhz with double data rate interface. Seeking comments...
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    Latest Version of PIPE!!

    Hi, Could anybody please tell me what the latest version of PIPE (Phy Interface for PCI Express) is? Thanks.
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    Looking for AMBA APB RTL

    Re: AMBA APB RTL? Hi, What exactly are you looking for when you say APB RTL? Regards.
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    Generating VCD with ncverilog

    ncverilog dumpfile Thanks a lot, Ajeetha and feel_on_on. It was quite helpful. Regards.
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    Generating VCD with ncverilog

    ncverilog vcd Hi All, Could anybody please tell me how to generate VCD file/database using ncverilog. A small tutorial will be of great help. Thanks & regards.
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    What is the difference between two code?

    Yes, as ankit said, first code has Asynchronous reset whereas the second one has Synchronous reset. Both the schemes are ok and both are supposed to work. When you say the second code didn't work, does it mean it didn't work in simulation or it didn't work on board? Well, one small thing...
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    Are CLBs and PEs the same??

    Xilinx calls main logic resource available on FPGA as CLB (Configurable Logic Block) whereas Altera call them LE (Logic Elements). Its just a matter of how they call it. Logically CLBs and LEs may be same but structurally they are different. By terminology, CLBs are available on XILINX FPGAs...
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    plz help me solve these erors in xilinx project

    error:ngdbuild:604 Hari, The code which you have given is not complete in the sense that there's no definitions for all the components declared. In a simpler way, you should have RTL code for all the components used. For example you are using "RegArray", "DataMux" etc. Your project should...
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    [REQ] ARM7TDMI TEST CHIP

    Yes, Speed is the major concern when we put ARM on FPGA. We have put ARM1176 on Virtex4. It doesn't go beyond 50Mhz. I wish you get ARM7tdmi chip with AHB interface. Warm Regards.
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    [REQ] ARM7TDMI TEST CHIP

    Hi, You can get the ARM processor code (RTL) from ARM under license agreement. And the RTL given by them is completely synthesizable. We have ARM1176 working on FPGA. Regards.

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