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Recent content by aaronhe

  1. A

    Clock domain crossing checks !

    Can spyglass read SDC? If not, I dont think it can do function CDC
  2. A

    Difference between sanded cell library provided by different library vendors

    What I've seen is performance difference. Every vendor's stdcell's performance is different.
  3. A

    ROM vs "Combination lookup table"

    No, ROM's dynamic power and leakage power are both lesser than "Combination lookup table" Added after 5 minutes: FFT usage, the data is not so simple as 255-0
  4. A

    ROM vs "Combination lookup table"

    Our project needs some high speed ROM, but the ROM from many verndors can't meet our spec. So I try to make it with "Combination lookup table", just use standard cell. The results show that area and speed of "Combination lookup table" is better than ROM. Could anyone tell me some shortcoming...
  5. A

    how to fix the port address in place?

    I want to fix some ports' address of the module in the lefthand of die , and the other in righthand. How to reach it ? Which cmd should I use ? thanks in advance.
  6. A

    weakness of formal verification

    fm verification is just one node of total verification. Function verification, fm_verificaion, physical verification and back_annoted verification. In my opinion, fm verification is used to be sure the consistent of your RTL code and synthesised netlist
  7. A

    library_setup_time puzzle

    The followint is a slice of timing library. ......... pin(D) { direction : input; nextstate_type : data; related_ground_pin : VSS; related_power_pin : VDD; capacitance : 0.0009724; rise_capacitance : 0.0009724; fall_capacitance : 0.0009669; timing () {...
  8. A

    how to break timing loops?

    It's solved. I track tese loops and add DFF to breake them.
  9. A

    how to break timing loops?

    I found there are two timing loops after synthesis. As following: Pin (timing loop #1) -------------------------------------------------- U5/ZN crossbar/vc_req_dec/U9/A1 crossbar/vc_req_dec/U9/ZN crossbar/vc_req_dec/U27/I crossbar/vc_req_dec/U27/ZN crossbar/vc_req_dec/U28/I...
  10. A

    Logic Synthesis for small rtl, correct synthesis netlist

    Logic Synthesis If you have spyglass, you can run it to check your netlist's robustness
  11. A

    How to combine many SDF to one under Prime Time ?

    I want to combine 4 SDF in to one to do OCV STA. Which command can finish it under prime time? The 4 SDF are caculated from Cmax spef, Cmin spef, RCmax spef and RCmin spef. Thanks for your reply. Happy weekend.
  12. A

    high speed ROM requirement

    Our project need some high speed ROM (> 400Mhz); I've evaluated tsmc's , arm_for_chartered's and virage's ROM. they are all about 200MHz; Who can give me some IP vendor list which can support high speed ROM ? What about Sidense ? Thanks for your advise
  13. A

    Analog IO VS Digital IO ?

    Do you mean analog IO can accept analog sequential signals, but Digital IO just can accept digital gignals (1 and 0) ?
  14. A

    Analog IO VS Digital IO ?

    Who can tell me the difference between Analog IO and Digital IO? I'm puzzle on them. Thanks a lot
  15. A

    what is the output of mux if select is X

    I think In real world. the output can't be decided if the select signal can't be decided; In library, it depends on model. I checked tsmc and arm library, there are no this "X" situation of select signal.
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