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Recent content by a_mythpi

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    Minstep Violation in SOC encounter

    Hello. I get a certain "Minstep Violation" when i run verify geometry for my design (violation is in the full custom cell I have designed) with same cell violations disallowed. Can anyone please explain me what exactly is this violation and how it can be fixed? Cheers Amith
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    SOC encounter Power Ground Pins Routing

    Hello, I am trying to do the power routing of the IO pads in my design. I connected all the power and ground pins using global net connect command. globalNetConnect vdd -type pgpin -pin {vdd} -inst * -module {} globalNetConnect vdd -type pgpin -pin {vdds} -inst * -module {}...
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    SOC encounter Routing power pins of the IO pads

    Hi. How do you connect the pins Manually? I mean which metal is to be used and also I donot know how to use SOC encounter tools to manually create metal layers. to connect them
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    SOC encounter Routing power pins of the IO pads

    Hello. thank you for your reply. I have around 100 pads out of which 16 are power / ground pads. How do I route this to the power rings outside my core design manually. Also I see in the design browser that there are a number of p/G nets for every IO pad. How do I route these pins...
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    SOC encounter Routing power pins of the IO pads

    Hello, Can anyone please advice me on the routing of power pins in the IO pads. I used the global net connect command to connect the power pins to net vdd and net gnd. Then I tried sroute with pad pins. But I am getting hole violations . I am not really sure the order in which the routing must...
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    SOC encounter CTS and routing

    Thank you for the reply. Actually, when I do optimisation -preCTS it adds buffers to the clock and hence if I run run CTS for the Clock net I get only a partial clock tree till the first buffer is placed
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    SOC encounter CTS and routing

    Hello, i have some doubts regarding clock tree generation and routing. I am just a beginner in this field, so certain question might seem trivial: 1. Is the CTS done before the routing process or after the routing process. 2. I was trying the optimisation option in SOC encounter before...
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    gnd and vdd pins removed after gatelevel synthesis

    Hello.. I have certains full custom cells for which I have defined a verilog interface ( just a black box). They have gnd and vdd as input pins. This verilog module is instantiated many times in a higher level verilog module. When i try to generate a flatened gate level netlist using design...
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    Design Compiler Segmentation Fault

    Hello... I am running it on the server which has sufficient memory . I believe memory shold not be a problem in this case.
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    Design Compiler Segmentation Fault

    Hello.. I am trying to obtain a gate level netlist for my rtl code. I have two versions of the same design. One is a larger version of the same design. I am able to obtain the gate level netlist for the smaller design ( runs for around 8-9 hrs) but when I do the same for the other one it gives...
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    [SOLVED] N variable Karnaugh Maps

    He asked for number of variables... not no. of terms..
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    [SOLVED] N variable Karnaugh Maps

    N-2 must be the answer I guess
  13. A

    pad insertion netlist for soc encounter

    Hi, No. As far as I know the filler cells cannot overlap each other. Try this: 1. Prepare a rough floor plan by giving only the cell utilisation and the ratio 2. Check the total width of the floorplan. By total width I mean including the IO pads 3. Now readjust the Length or width according...
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    Dummy Pins short errors IO corner pads

    Hello, I donot have much Experience in Place and route operation. The problem is that I have completed the place and routing of the core area as well as the IO pads. When I run DRC verify geometry I have no violations in the core area but in the Corner IO pads I get two short erros (...
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    SOC encounter Filler cell short errors

    Hello people! I am trying to do floor planning for my design for the first time. Actually I have done the basic fllorplanning and have placed the i/o pads as well but not the macro cells ( placement in the core area) yet. I verified the geometry after this step and found a lot of spacing...
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