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Recent content by 94d33m

  1. 9

    Resistor starting from Metal5 in tsmc5/4

    Yeah, TSMC 5nm and TSMC 4nm nodes There were layers like RH_TNB , RH_TN, and then on top of that, Metal 5 on both ends, which vias upto Metal 6
  2. 9

    Resistor starting from Metal5 in tsmc5/4

    So while I was working for layout in Tsmc 5/4 I encountered something that I didn't before, at any other node. Here the resistor started from M5/M6 so you could place logic devices under them(but you cannot route on M5/M6 on the resistor area and cannot have M5M6 powergrid there as well ). Any...
  3. 9

    Why isn't a flip chip an industry standard that chip designs should use ?

    Considering that flip chip has bond pads below substrate so we can route power from bottom side and do routing on top side, isnt it so much better? What are the issues ?
  4. 9

    In which region does the BJT operate during latchup condition? Saturation or Active?

    A
  5. 9

    In which region does the BJT operate during latchup condition? Saturation or Active?

    Will latchup still occur? Or will it be intensified instead?
  6. 9

    Tanner L-Edit , How to name a wire for easy recognition?

    Ah This is cadence virtuoso.....if you click the node it already shows in navigator :p. Tanner lacks this feature only otherwise it's great
  7. 9

    Tanner L-Edit , How to name a wire for easy recognition?

    Normally what we do is place text labels on top of the wire, but if the wire is very long then we have to pan to the text part to see what net it is. Is there any way to name a node ?
  8. 9

    Why do we need a power splitted transistor ? (Analog layout)

    I heard in advanced nodes where the voltage is very low, if we share the VDD diffusion with two transistors , we can have an IR issue. But why is this ? Isnt the voltage same regardless of whether we share the diffusion or not ?
  9. 9

    Why is pmos and nmos put vertically and not side by side(horizontally)in ic layouts?

    Is it because of convention or because wires would be longer ?
  10. 9

    'Process interrupted by signal SEGV' ( in atlas, solar cell code for quantum well )

    So my thesis is on solar cell quantum well.....unfortunately the codes we got had an problem in spacing and after fixing it I only found that adding quantum wells decreases efficiency and never the other way around. But now i added two new models called 'models well.capt well.inplane' and the...
  11. 9

    Which will be a faster circuit?

    If i create a circuit using behavioural model and another using structural model...then after synthesis will the structural model be faster?
  12. 9

    Why do electrons move from p to n in solar cell but from n to p in normal diode?

    The n region already has alot of electrons so i dont see the reason......If a photon frees an e- from p region, cant they just go out from that side? Is it because of the electric field from the depletion layer? But the depletion layer isnt throughout the whole length right, so what drives them...
  13. 9

    CMOS fabrication - why do we use a p+ substrate trap and n+ well trap ?

    I have tried searching google about this, and Im surprised to see no matching results on this trap thingy...
  14. 9

    How does this function work for displaying string in lcd?

    and does lcd_char(*p++) mean it sends the value to the function first then increases its value ??
  15. 9

    How does this function work for displaying string in lcd?

    lcd_string("welcome"); void lcd_string(unsigned char *p) { while(*p!=0) { lcd_char(*p++); } } void lcd_char(unsigned char cha) { lcd_data_port=cha; rs=1; rw=0; en=1; delay(10); en=0; } How does the function lcd_string work?
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