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I have written a verilog file that implements some arithmetic operations, I defined my signals as wire signed or reg signed. when I simulate that on isim simulator it does the operation as specified, with signed arithmetic. but when I simulate the same file in modelsim it behaves as if the...
I'm using design compiler to generate a clock as following:
create_generated_clock -multiply_by 1 -duty_cycle 15 -source CLKIN_X2 [get_ports MUX5/sel]
this should create a %15 duty cycle clock and tie it to MUX5/sel but it doesn't. in my netlist MUX5/sel is connected to ground. why?
I'm using synopsys DC to synthesize a design, the compilation finishes with no errors, also all warnings are reasonable (unconnected signals and so).
the problem is when I check the verilog netlist I find GTECH cells! most cells are mapped to library cells as normal, but there are some unmapped...
I'm new to static timing analysis, I have been reading Prime Time's user guide before actually using it. Most commands mentioned are shared with Design Compiler, and the user guide says that most shared commands are either identical or have slight differences.
my questions are why do I have to...
I'm using Design Compiler in Topographical Mode and making manual floorplanning for my designs as this is better than using WLMs. The design contains a Register File which I simply floorplanned using these simple commands:
set_aspect_ratio .5
set_utilization .85
set_port_side [all_inputs] -side...
I wanted to estimate the power consumption of a design. I'm using Synopsys Power Compiler,Design Compiler and Modelsim.
I first used the lib2saif command in DC to generate a SAIF file (also found lots of tutorials mentioning rtl2saif command, seems to be obsolete though,command is unknown in...
I'll describe what I'm trying to do briefly, maybe it can help.
I have this open source DDR3 Controller which is written for Xilinx Spartan FPGAs. and I'm trying to translate it to some form that is suitable for ASIC synthesis tools.
The file relies heavily on Xilinx's ISERDES2 and OSERDES2 for...
How to describe a Double Data Rate (DDR) Register in VHDL ??
I tried a process like this :
process(Input_Clk,Input_Data,Reset_Control)
begin
if (Reset_Control = '1') then
Output_Data <= (others => '0');
elsif (Input_Clk'event) then
Output_Data <= Input_Data;
end if;
end process...
How to move data between different clock domains? possibly Single and Double data rates too.
I know a dual clock FIFO could be used for that purpose. but it is not needed!!
the design is a counter running in one clock domain and writing the value to a register, and the value is read in another...
Problem solved.
I was using $MODELSIM=/PATH/TO/INSTALLATION in my .bashrc file.
modelsim looks for the license file in $MODELSIM=/PATH/TO/LICENSE.dat and if not found it uses the original one in the installation. setting the path to the right file solves the problem.
The libraries were working fine until one time they are just not there !!
I have not changed the modelsim.ini file in any way, But after the problem appeared I have tried to create an environment variable $MODEL_TECH (the one found in modelsim.ini) and map it to my installation folder and to...
I started modelsim to find no libraries loaded,not even IEEE standard libraries, only my work library that I added using vlib but nothing more.
The libraries list in gui is empty.
Is there something wrong with my modelsim.ini file ?? the file is located at $modeltech and I haven't changed or...
How are the chips organized on a typical DDR3 memory module used in PCs ??
I'm not asking about the organization of rows and columns inside memory chips, I'm asking about the connections between these chips and the bus. Do they share the same bus (while each has a 4,8 or 16 data width)?? or is...
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