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Recent content by 214

  1. 2

    storing values from vhdl wave

    What if i have more data and we have to write them in one single line(like 100 sfixed values) and after every 10 values we have to put a comma sign
  2. 2

    storing values from vhdl wave

    can u please write a sample code for me.... I am really stuck with this kind of output values. thanks in advance
  3. 2

    storing values from vhdl wave

    but how it will be saved in my system.... in which format. I want the output values in text file. so that i can reconstruct it in MATLAB
  4. 2

    storing values from vhdl wave

    I want to write the values(sfixed ) in text file
  5. 2

    storing values from vhdl wave

    i need to store the values in text file. Is it not possible directly from the waveform itself ? since all values are in sfixed format, it will be very difficult....
  6. 2

    storing values from vhdl wave

    my output values are displayed in vhdl wave window. I s there any possible way to store values directly from this wave window ???
  7. 2

    converting sfixed to std_logic_vector

    i want to convert sfixed number (12 down to -8) to std_logic_vector.... what could be the possible command for use ?
  8. 2

    [SOLVED] simulation stops after 1 clock

    for 31700 ns...timeperiod is 100ns
  9. 2

    [SOLVED] simulation stops after 1 clock

    the test bench is as follows: -------------------------------------------------------------------------------- LIBRARY ieee; LIBRARY std; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.numeric_std.ALL; USE std.textio.ALL; USE work.edge_package.ALL; -- Uncomment the...
  10. 2

    [SOLVED] simulation stops after 1 clock

    LIBRARY IEEE; USE ieee.std_logic_1164.all; --USE ieee.std_logic_arith.all; USE ieee.numeric_std.all; library ieee_proposed; use ieee_proposed.fixed_pkg.all; ENTITY dwt IS PORT ( clk : IN STD_LOGIC; vid_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Pixels from main memory...
  11. 2

    multiplying unsigned number and sfixed number

    Multiplication using sfixed numbers in vhdl I am trying to multiply an unsigned number with sfixed number (0.703125). following are the code and errors: library IEEE; use IEEE.STD_LOGIC_1164.ALL; library ieee_proposed; use ieee_proposed.fixed_pkg.all; USE ieee.numeric_std.all; entity...
  12. 2

    multiplying unsigned number and sfixed number

    how can i multiply an unsigned number with a sfixed number (for eg 0.703125) ?? should i convert the unsigned into sfixed type and carry on with multiplication ? i want the result of the multiplication back in unsigned format.. thanks in advance
  13. 2

    array assignment in vhdl with signed numbers

    TYPE buf_ary_d IS ARRAY (NATURAL RANGE <>) OF SIGNED(7 DOWNTO 0); will it work for my case ???
  14. 2

    array assignment in vhdl with signed numbers

    sorry....can you make this explanation simpler.....i did not understand this
  15. 2

    libraries in modelsim in vhdl

    i have used the following libaries LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.numeric_std.all; still the error in modelsim shows : ** Error: G:/vhdl code/vhdl code/dwt_main.vhd(30): (vcom-1078) Identifier "UNSIGNED" is not directly visible...
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