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Recent content by 1189raji

  1. 1

    what is the reason behind op-amp symbol?

    Hi, Thank you for your response but still i couldn't able to get why the symbol is so? i think there will be some reason behind it??
  2. 1

    what is the reason behind op-amp symbol?

    Hi friends, Can anyone help me out of this question.Why op-amp symbol is triangle in shape. regards, rajeshwari 1189raji@gmail.com
  3. 1

    Setting directory path in installscape

    Hi friends, i am trying to download MMSIM7.1 from cadence site but its showing error in directory path,how to solve this issue.
  4. 1

    i need SOI CMOS model parameters in 180nm technology

    Hi friends, Can anyone help me to find the SOI cmos model parameters in 180nm technology because at present i am working in SOI concept if anyone send the SOI model parameters then it will help me lot to finish my project. rajeshwari.vlsi@gmail.com
  5. 1

    Is it possible to use array multiplier for driving large load with BICMOS logic?

    Hi friendz, I am doing my project in Backend and i am trying to implement BICMOS logic for array multiplier.Generally bicmos is to drive large load.Since i am trying array multiplier with bicmos logic i donno where this multiplier going to drive load.So if anyone knows application plz post...
  6. 1

    [MOVED] BJT model parameter in 180nm technology

    hi friends, If anyone have SPICE BJT model parameter in 180nm technology pls post here or send to my mail id 1189raji@gmail.com or rajeshwari.vlsi@gmail.com because i am trying to do project in HSPICE and i am finding difficulties to get model parameter in 180nm tech.Pls let me know as...
  7. 1

    analysis of bicmos circuit in cadence environment

    hi friends, Which analysis i should perform in order to plot current vs time graph in cadence.Plz let me know as soon as possible.
  8. 1

    Please help to create finfet symbol in cadence

    i doesnt have any model file so i stuck up with start dont know how to proceed
  9. 1

    Please help to create finfet symbol in cadence

    thank you for your response but finfet has double gates right then howcome its possible to edit mosfet symbol
  10. 1

    Please help to create finfet symbol in cadence

    hi friends, Iam having idea to do project in finfet at cadence.Is there any finfet symbol and model library is available in cadence???Please anyone guide me to create symbol
  11. 1

    what do you mean my 45nm in vlsi?

    thank you so much!!!!!!!!!!
  12. 1

    CAD tools and algorithms for those tools

    thank you for your reply but still i didnt clear friend actually my sir said totally there are 64 CAD tools are available for designing vlsi circuit it seems i want to know what those 64 tools are??????
  13. 1

    what do you mean my 45nm in vlsi?

    hi friends, Anyone explain clearly what's that 45nm technology in vlsi?
  14. 1

    CAD tools and algorithms for those tools

    hi friends, i need to know what are the different cad tools are available for designing an vlsi circuits and what are the algorithms are used for those tools if anyone knows plz kindly let me know.
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