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abimann
abimann
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12th April 2018,
18:25
abimann
replied to a thread
Edge detection, which parameter used for get autofocus working ?
in
PLD, SPLD, GAL, CPLD, FPGA Design
no good experience in vhdl when so many edges , it mean camera best focused, so I think need to just invert data and summ for every frame.. pls...
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6 replies | 440 view(s)
9th April 2018,
07:33
abimann
replied to a thread [SOLVED]
Verilog error , Pls help
in
PLD, SPLD, GAL, CPLD, FPGA Design
ads-ee, I use new directory create file and only copy sources, BRAM ips are generated for Virtex-4 only .. when i use wire instead reg it also...
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13 replies | 1121 view(s)
25th March 2018,
13:17
abimann
replied to a thread [SOLVED]
Verilog error , Pls help
in
PLD, SPLD, GAL, CPLD, FPGA Design
Dear all , i made screenshot , brams are made for Virtex-4 not for Spartan6. this exactly based on fpga chip error
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13 replies | 1121 view(s)
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PLD, SPLD, GAL, CPLD, FPGA Design
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