• Yesterday, 19:00
5 replies | 104 view(s)
• Yesterday, 18:28
Simply your equation is wrong. You have to apply imag() for numerator. Generally Capacitance is nearly constant over frequency.
5 replies | 104 view(s)
• Yesterday, 17:15
5 replies | 104 view(s)
• Yesterday, 16:31
Load current could be sink and source direction. So simple DC current source is not appropriate as load.
7 replies | 85 view(s)
• Yesterday, 16:06
Simply do load value sweep with observing THD or SNDR. However load could be capacitive.
7 replies | 85 view(s)
• Yesterday, 15:37
Simply edit manually.
3 replies | 67 view(s)
• Yesterday, 14:41
Simply they are bus pins.
3 replies | 67 view(s)
• Yesterday, 14:15
No one can understand what you mean. Express in detail with correct terminology. Do you mean Gate-Level-HDL which is synthesized from RTL-HDL ?
3 replies | 186 view(s)
• 16th September 2019, 17:24
Show me netlist regarding signal sources, loads, balun and analysis statements.
22 replies | 869 view(s)
• 15th September 2019, 20:11
Yes........
3 replies | 159 view(s)
• 15th September 2019, 20:06
Why do you set three ports. Where is driving point ? What do you expect ?
1 replies | 88 view(s)
• 15th September 2019, 19:55
Assume three mobile phones, A, B and C. Their Distances from base station are different. Distance of A is small. Distance of B and C is large. ...
3 replies | 159 view(s)
• 12th September 2019, 14:12
This is not transparent latch. For V(Clk2)=High, V(out)=V(in) ; Tranparent Then V(in) is captured at negative edge of V(Clk2). V(out) is...
7 replies | 292 view(s)
• 12th September 2019, 13:51
15 replies | 513 view(s)
• 12th September 2019, 07:03
Can you understand netlist ? Show me netlist.
15 replies | 513 view(s)
• 12th September 2019, 01:53
This is a static DNL. Evaluation of static DNL and INL does not require Histogram. On the other hand, dynamic DNL requires Histogram.
2 replies | 214 view(s)
• 12th September 2019, 01:32
First of all, you have to learn INL and DNL before EDA Tool Play. That's all.
7 replies | 424 view(s)
• 11th September 2019, 18:51
No. You can not understand Verilog-A at all. if V(clk2) >=0 aho = V(in); @cross(V(clk2), -1) aho = V(in); V(out) <+ aho;
7 replies | 292 view(s)
• 11th September 2019, 18:45
Your code is not differential amplifier. analog begin vdiff = V(sigin_p) - V(sigin_n); V(sigout_p) <+ vdiff * gain / 2 + vcom V(sigout_n)...
4 replies | 201 view(s)
• 11th September 2019, 17:05
Use @cross().
7 replies | 292 view(s)
• 11th September 2019, 14:30
Can you undestand your circuits ? DC Analysis is not useful. You have to do Transient Analysis or Shooting-Newton-PSS Analysis. Show me...
15 replies | 513 view(s)
• 11th September 2019, 12:59
Too easy. Vout=Vdd - L*dI/dt Surely learn very basic things before EDA Tool Play.
2 replies | 209 view(s)
• 11th September 2019, 10:25
It is a design framework.
15 replies | 513 view(s)
• 11th September 2019, 07:58
What switch do you use in switched capacitor circuit ? Is it MOSFET or behavioral ideal switch ?
4 replies | 201 view(s)
• 11th September 2019, 06:10
Cadence have many many tools. No one knows what tool you use.
15 replies | 513 view(s)
• 10th September 2019, 19:30
What do you want to mean by “same effect” ? If you mean an equivalency as signal processing, RL=5kohm, CL=20pF.
22 replies | 869 view(s)
• 10th September 2019, 18:57
Consider common mode for floating load case. Load is infinity for common mode.
22 replies | 869 view(s)
• 10th September 2019, 18:26
Load of method1 is floating load not differential Load. There is no common mode load. So method1 is not equivalent to both method2 and method3....
22 replies | 869 view(s)
• 10th September 2019, 16:20
I don't think so. Method1 : Vo_diff = (Uo+-Uo-) + VCM Method2 : Vo_diff = (Uo+-Uo-) VCM is not required in method1. Surely consider direction of...
22 replies | 869 view(s)
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