joniengr
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Yesterday, 07:06Hi, I guess it is ok to sample the ADC data at both positive and negative edges in FPGA, right ? Do the FPGA or ZYNQ have LVDS I/O to take the...3 replies | 182 view(s) -
18th October 2019, 16:54Hi, I am considering AD9257 ADC for my application. The ADC chip is octal which means 8 ADC on chip. The resolution is 14 bits and sampling rate...3 replies | 182 view(s)
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22nd September 2019, 08:11Hi, I guess UART-USB bridge is USB CDC class which is limited by the data rate close to Low Speed 1.5 Mbps. Is this limitation of UART or...3 replies | 424 view(s)
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21st September 2019, 20:18Hi, I am trying to understand the connection between the two USB classes CDC and HID and four types of following data transfers. Control...3 replies | 424 view(s)
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21st September 2019, 20:12Actually I have PIC18F2550 in house and PIC programmer. For learning purpose I would like to start working with that. The aim is to get throughput of...6 replies | 411 view(s)
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21st September 2019, 14:28Thanks for your reply. I guess I would go with 50 kilo sample per second at the first stage and consider USB Full Speed for communication. -...6 replies | 411 view(s)
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21st September 2019, 08:29Actually I need to sample a pulse from accelerator meter which is around 1 to 5 ns. I need to sample the peak value. I am looking for peak hold...3 replies | 282 view(s)
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20th September 2019, 08:23Hi, I would like to capture a jitter of 1 ns. I am looking for sample and hold IC which can hold the peak up to 1 micro second or more. Is there...3 replies | 282 view(s)
About joniengr
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Areas of Interest
- Area of specialization:
- Analog Circuit Design, Electromagnetic Design and Simulation, PLD, SPLD, GAL, CPLD, FPGA Design, Microcontrollers, PCB Routing / Layout / SImulation
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20th October 2019
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19th October 2019
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22nd September 2019
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20th September 2019
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19th September 2019
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