ranayehya
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- 7th September 2018 17:25
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3rd September 2018, 15:10ranayehya replied to a thread Working with sparten 3e starter board in PLD, SPLD, GAL, CPLD, FPGA DesignI added a schematic file to my project and selected "View HDL Functional Model" option from design menu and it gives me (schematic file name.vhf)...17 replies | 593 view(s) -
3rd September 2018, 14:43ranayehya replied to a thread Working with sparten 3e starter board in PLD, SPLD, GAL, CPLD, FPGA DesignWhen I saw tutorials on YouTube about programming the kit, there was 3 JTAG devices in videos and the kit in the videos was programmed This are the...17 replies | 593 view(s)
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3rd September 2018, 14:27ranayehya replied to a thread Working with sparten 3e starter board in PLD, SPLD, GAL, CPLD, FPGA DesignThis is what I have done a while ago and I did it again today but the kit did nothing.17 replies | 593 view(s)
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3rd September 2018, 14:25ranayehya replied to a thread Working with sparten 3e starter board in PLD, SPLD, GAL, CPLD, FPGA DesignI edited in constraint file Mr.KlausST and nothing changed. NET "z" LOC = "E12" |IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "x" LOC = "N17"...17 replies | 593 view(s)
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3rd September 2018, 14:23ranayehya replied to a thread Working with sparten 3e starter board in PLD, SPLD, GAL, CPLD, FPGA DesignYes, Mr.Barry. I said that17 replies | 593 view(s)
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2nd September 2018, 18:02ranayehya replied to a thread Working with sparten 3e starter board in PLD, SPLD, GAL, CPLD, FPGA DesignSorry Sir. TrickyDicky but I do not get your question very well Are all LEDs operate when they get voltage? I took an image from datasheet17 replies | 593 view(s)
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2nd September 2018, 16:32ranayehya replied to a thread Working with sparten 3e starter board in PLD, SPLD, GAL, CPLD, FPGA DesignThe constraint file consists of 2 switches and a LED in the board. I switched it on and off and the LED did not work.17 replies | 593 view(s)
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2nd September 2018, 13:28ranayehya started a thread Working with sparten 3e starter board in PLD, SPLD, GAL, CPLD, FPGA DesignHello All! I am starting my first project(an and gate) with the kit mentioned above and ISE design suite The flow run smoothly. But in the end, the...17 replies | 593 view(s)
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2nd September 2018, 10:44Do you mean that I should put clock and reset?10 replies | 497 view(s)
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2nd September 2018, 09:07Thanks vGoodtimes for your comment but I have another question. How to know that my tool will implement my rom as a rom? I am using vivado 5.110 replies | 497 view(s)
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1st September 2018, 21:54I think it is a 3D array and also I read in tutorials on verilog that initial block does not use in verilog10 replies | 497 view(s)
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1st September 2018, 21:35Hello All! I am trying to write a 2D ROM in verilog it is 16 * 16 and each element has 1 byte I have felt a little bit dizzy about all websites I...10 replies | 497 view(s)
About ranayehya
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- Area of specialization:
- ASIC Design, PLD, SPLD, GAL, CPLD, FPGA Design, Microcontrollers
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4th September 2018
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3rd September 2018
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2nd September 2018
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17th June 2018
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