ranayehya
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26th November 2018, 15:23ranayehya replied to a thread [SOLVED] Instantiating module with inout in PLD, SPLD, GAL, CPLD, FPGA DesignThanks to you all for commenting. It works when I write it in that way. assign sda = enable? sda_reg : 1'bz;4 replies | 191 view(s) -
26th November 2018, 11:25ranayehya replied to a thread [SOLVED] Instantiating module with inout in PLD, SPLD, GAL, CPLD, FPGA DesignHello, FvM! In the first image, "enable" signal was = 1. So sda = sda_reg and that works In the second image, "enable" signal was = 1. sda should...4 replies | 191 view(s)
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26th November 2018, 08:03ranayehya started a thread [SOLVED] Instantiating module with inout in PLD, SPLD, GAL, CPLD, FPGA DesignHello! I am new in verilog and I begin working on I2C protocol hardware implementation The master code works well but when I combine all files...4 replies | 191 view(s)
About ranayehya
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- ASIC Design, PLD, SPLD, GAL, CPLD, FPGA Design, Microcontrollers
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27th November 2018
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20th October 2018
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19th October 2018
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15th October 2018
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14th October 2018
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12th October 2018
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