Puppet123
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31st October 2019, 12:19Puppet123 started a thread TSMC65nm CRN65LP PDK Calibre and PEX Issues in Analog Integrated Circuit (IC) Design, Layout and FabricationHello, I am having some issues with TSMC65nm CRN65LP PDK Calibre and PEX Issues - mainly setitng up PEX for Calibre and TSMC65nm CRN65LP PDK for...1 replies | 137 view(s) -
31st October 2019, 11:25Puppet123 replied to a thread Physical Verification with TSMC65nm CRN65LP PDK in Analog Integrated Circuit (IC) Design, Layout and Fabricationno one uses tsmc65nm PDK here ?2 replies | 310 view(s)
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27th October 2019, 04:28Puppet123 replied to a thread How to measure the C parasitic (internal capacitance) of an inverter using Spectre ? in ASIC Design Methodologies and Tools (Digital)This value has to be derived from simulation. I understand properly - you just dont know the answer. Also, Cadence Spectre is a simulator. ...17 replies | 1196 view(s)
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27th October 2019, 04:17Puppet123 replied to a thread How to measure the C parasitic (internal capacitance) of an inverter using Spectre ? in ASIC Design Methodologies and Tools (Digital)You are right - this is an inverter driving another inverter. I am looking for Cpar - which is the capacitance of the driving inverters internal...17 replies | 1196 view(s)
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27th October 2019, 00:21Puppet123 replied to a thread How to measure the C parasitic (internal capacitance) of an inverter using Spectre ? in ASIC Design Methodologies and Tools (Digital)Please see attached picture for inverter. I am looking to measure Cpar = Cw in that picture. Cpar being the parasitic capacitance. - - -...17 replies | 1196 view(s)
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26th October 2019, 14:35Puppet123 started a thread How to measure the C parasitic (internal capacitance) of an inverter using Spectre ? in ASIC Design Methodologies and Tools (Digital)I want to measure the Reff of an inverter. I know how to measure the Cgate of the inverter. But how do I get the Cpar of the inverter (that...17 replies | 1196 view(s)
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12th October 2019, 02:48Puppet123 replied to a thread Need documets related to extraction of Inductance using Cadence Assura in Analog Integrated Circuit (IC) Design, Layout and FabricationJust use EM simulation. You would need an interface between Cadence (if you are using that) and Keysight ADS - it is called GoldenGate for Keysight...4 replies | 576 view(s)
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12th October 2019, 02:35Puppet123 replied to a thread NCSU FreePDK 15nm for Analog Design in Analog Integrated Circuit (IC) Design, Layout and FabricationThere is always Cadence's General Purpose PDK's, for using the flow of their software and tools and yes, they have a FINFET GPDK.2 replies | 325 view(s)
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12th October 2019, 02:29Puppet123 replied to a thread CMOS FINFET Layout Tutorials/Explanations in Analog Integrated Circuit (IC) Design, Layout and Fabricationi just want to learn how to do it. also not all PDKs offer "any help" or tutorials - especially on how to do layout. i am going to answer my own...9 replies | 814 view(s)
About Puppet123
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