Puppet123
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15th October 2019, 16:36Puppet123 replied to a thread Plotting of VCO output power vs frequency in cadence spectre in Analog Integrated Circuit (IC) Design, Layout and Fabricationgoogle it on internet3 replies | 181 view(s) -
12th October 2019, 02:48Puppet123 replied to a thread Need documets related to extraction of Inductance using Cadence Assura in Analog Integrated Circuit (IC) Design, Layout and FabricationJust use EM simulation. You would need an interface between Cadence (if you are using that) and Keysight ADS - it is called GoldenGate for Keysight...4 replies | 437 view(s)
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12th October 2019, 02:35Puppet123 replied to a thread NCSU FreePDK 15nm for Analog Design in Analog Integrated Circuit (IC) Design, Layout and FabricationThere is always Cadence's General Purpose PDK's, for using the flow of their software and tools and yes, they have a FINFET GPDK.2 replies | 233 view(s)
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12th October 2019, 02:29Puppet123 replied to a thread CMOS FINFET Layout Tutorials/Explanations in Analog Integrated Circuit (IC) Design, Layout and Fabricationi just want to learn how to do it. also not all PDKs offer "any help" or tutorials - especially on how to do layout. i am going to answer my own...9 replies | 527 view(s)
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10th October 2019, 19:00Puppet123 started a thread CMOS FINFET Layout Tutorials/Explanations in Analog Integrated Circuit (IC) Design, Layout and FabricationWhat are the best resources (papers, books etc) to learn FINFET layout ? Can anyone share any ?9 replies | 527 view(s)
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7th October 2019, 21:43Puppet123 started a thread NCSU FreePDK 15nm for Analog Design in Analog Integrated Circuit (IC) Design, Layout and FabricationHello, Has anyone used this NCSU kit for Analog Design ? Or is it mainly for digital design (standard cell flow). Thank you.2 replies | 233 view(s)
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2nd October 2019, 14:55Puppet123 replied to a thread Decoupling Capacitance in IC Layo in Analog Integrated Circuit (IC) Design, Layout and FabricationTo this point, I have a few questions. When doing over 10 GHz amplifier designs, I usually tend to EM simulate the supply lines to determine the...5 replies | 570 view(s)
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30th September 2019, 23:45Puppet123 replied to a thread Decoupling Capacitance in IC Layo in Analog Integrated Circuit (IC) Design, Layout and FabricationSo you just add as much decoupling as you can depending on your layout at the IC level ? Just any amount ? - - - Updated - - - --5 replies | 570 view(s)
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28th September 2019, 05:03Puppet123 started a thread Decoupling Capacitance in IC Layo in Analog Integrated Circuit (IC) Design, Layout and FabricationIf doing an analog or RF layout, how much decoupling capacitance do you use in the layout for supply decoupling and, for RF layout, for supply feed...5 replies | 570 view(s)
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26th September 2019, 23:45Puppet123 replied to a thread Spice .INC file into Cadence Spectre/DFII in Analog Integrated Circuit (IC) Design, Layout and FabricationWhat if I have no model file chain and this is all I am using ?3 replies | 232 view(s)
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26th September 2019, 22:34Puppet123 started a thread Spice .INC file into Cadence Spectre/DFII in Analog Integrated Circuit (IC) Design, Layout and FabricationHello, I have a spice model for a process in .INC format. How can I use this file to do simulation using Cadence Spectre ? I would assume...3 replies | 232 view(s)
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23rd September 2019, 21:22Puppet123 started a thread Length of Path in Cadence Virtuoso/DFII in Analog Integrated Circuit (IC) Design, Layout and FabricationHello, I have a non straight, meandered line/path in Cadence Virtuoso/DFII. Is there a command to measure the length of this path ? Thank...1 replies | 177 view(s)
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23rd September 2019, 17:11Hello, Want to install Incisive add on to Cadence DFII using Installscape on Centos 6. Do I tell Installscape where DFII installation is...0 replies | 1677 view(s)
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18th September 2019, 14:51Puppet123 replied to a thread Converting verilog code into a symbol during AMS simulation in Analog Integrated Circuit (IC) Design, Layout and Fabricationhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-design/35255/easy-way-to-connect-a-input-bus-pins-in-schematic5 replies | 355 view(s)
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18th September 2019, 06:58Puppet123 replied to a thread Physical Verification with TSMC65nm CRN65LP PDK in Analog Integrated Circuit (IC) Design, Layout and FabricationNow I was told for my version of Calibre 2017, I have to do the following for this PDK: In LVS rule file add: LAYOUT CELL LIST pcells “rf...1 replies | 214 view(s)
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18th September 2019, 04:14Puppet123 started a thread Physical Verification with TSMC65nm CRN65LP PDK in Analog Integrated Circuit (IC) Design, Layout and FabricationHello, This posting is similar to an earlier posting: ...1 replies | 214 view(s)
About Puppet123
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