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Puppet123
Puppet123
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21st November 2019,
03:36
Puppet123
replied to a thread
SystemVerilog Behavioral Simulation in Cadence Virtuoso/AMS/Incisive/Spectre
in
ASIC Design Methodologies and Tools (Digital)
I know what .sv is. I am talking about analog / mixed signal simulation.
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2 replies | 266 view(s)
20th November 2019,
21:35
Puppet123
started a thread
SystemVerilog Behavioral Simulation in Cadence Virtuoso/AMS/Incisive/Spectre
in
ASIC Design Methodologies and Tools (Digital)
Hello, I want to do behavioral simulations using SystemVerilog as opposed to using Verilog-A and Verilog-AMS for Mixed Signal Designs in Cadence...
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2 replies | 266 view(s)
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