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About Anand Ranjith Mark

Basic Information

Date of Birth
July 14
Areas of Interest
Area of specialization:
Analog Circuit Design, PLD, SPLD, GAL, CPLD, FPGA Design
Optional Info
Occupation:
Design Engineer

Statistics


Total Posts
Total Posts
1
Posts Per Day
0.00
General Information
Last Activity
31st March 2015 06:12
Join Date
31st March 2015
Helpful Postings
 

Experience


Points
Points
21
Level
1
Points: 21, Level: 1
 
Level up completed
Level up completed
41%
Points required
29

Activity


Activity
0%
Activity last 30 days
0%
Activity last 7 days
0%

Points


All Points for user
Points for User
10
Points for Reputation
10
All Points for threads
Points for threads
3
Points for Threads
1
Points for Social Group Discussions
2
All Points for posts
Points for Posts
8
Points for Posts
6
Points for Social Group Messages
2
All Points for miscellaneous
Points for Misc
0

Activities