2010vl04
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Today, 16:49FvM replied to a thread Voltage degradation in Hold mode of the bootstrap switch ? in Analog Integrated Circuit (IC) Design, Layout and FabricationThe effect is called "hold step", happens due to switch charge injection, in other words Cgd respectively Cgs of the switch MOSFET.1 replies | 28 view(s) -
Today, 16:41FvM replied to a thread CMRR simulation for fully differential amplifier in Analog Integrated Circuit (IC) Design, Layout and FabricationIn practice, you don't need to measure differential mode gain to determine CMRR because it's defined by the feedback network with sufficient accuracy.8 replies | 118 view(s)
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Today, 16:37I would expect antiparallel diodes instead of two diodes with same polarity. What's your specification for the limiter (output versus input level,...1 replies | 21 view(s)
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Today, 12:08Industry standard level control relays for electrodes have adjustable threshold range, e.g. 1k - 100k resistance. It's suitable for drinking water,...7 replies | 328 view(s)
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Today, 09:02FvM replied to a thread CMRR simulation for fully differential amplifier in Analog Integrated Circuit (IC) Design, Layout and FabricationThink simple. To measure CMRR, you'll apply a common mode signal and measure the respective transfer function.8 replies | 118 view(s)
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Yesterday, 23:30There's much literature about oil and gas filled HV switches, some results can be probably applied to sparc gap behaviour. I agree with wwfeldman...8 replies | 210 view(s)
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Yesterday, 23:20FvM replied to a thread How to make a 5V negative supply using the LM2576 regulator in Analog Circuit DesignThe shown 200 mV noise is just what you can expect from the simple circuit and layout. The 80 MHz ringing is mostly caused by the switching schottky...4 replies | 128 view(s)
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Yesterday, 23:00I suggest to study high voltage ultrasonic echo sounder circuits to get an idea how to implement voltage clamping in the receiver path. They often...7 replies | 275 view(s)
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Yesterday, 22:11That's o.k. Problem is unsuitable combination of kp and ki, as already stated. kp=1 seems generally problematic. A controller with practical use has...5 replies | 170 view(s)
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Yesterday, 14:05In case of doubt, derive the parameters in transient analysis.6 replies | 144 view(s)
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Yesterday, 12:56FvM replied to a thread How to design an class d output filter ( active filter )? in Analog Circuit DesignPurpose of the design is still mysterious. You may use a SD-modulator to drive a three-level class D amplifier and place a passive LC filter towards...7 replies | 195 view(s)
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Yesterday, 12:45Please specify "control speed". - on/off control - switching between discrete speeds - continuous speed variation In addition, what's expected...4 replies | 143 view(s)
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Yesterday, 12:27FvM replied to a thread VHDL coding Status register read problem in PLD, SPLD, GAL, CPLD, FPGA DesignRegisters assigned on both edges are sreg(0), sreg(1), sreg(3), sreg(4), ISA_DBUS2. It's easy to see the signals assigned under falling and rising...4 replies | 178 view(s)
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17th March 2019, 22:31Right. XOR detector transfer function is a triangle for square wave signals. Depending on the VCO slope sign, the PLL either locking on the rising or...7 replies | 246 view(s)
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17th March 2019, 19:26FvM replied to a thread PCB design and schematic for a half bridge power amplifier. in PCB Routing Schematic Layout software and SimulationThe driver circuit is wrong, you can't drive a 24V supplied PMOS transistor with a 12 V ground referred driver. Q2 will be permanently on.5 replies | 189 view(s)
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17th March 2019, 12:26Thick film jumper resistor have finite resistance (at least a few milliohms) and thus limited current capability. The nominal current rating of a...1 replies | 107 view(s)
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17th March 2019, 10:42FvM replied to a thread How to design an class d output filter ( active filter )? in Analog Circuit DesignSeriously I don't understand the purpose of an active filter behind a class D amplifier. Nevertheless a linear filter with almost flat pass band...7 replies | 195 view(s)
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17th March 2019, 10:18FvM replied to a thread Using Plain polyester or Metalized polyester Capacitor in place of polypropylene in Power ElectronicsIf they are rated for 250VAC (or whatever the applied AC voltage is) ...2 replies | 151 view(s)
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17th March 2019, 10:14FvM replied to a thread PCB design and schematic for a half bridge power amplifier. in PCB Routing Schematic Layout software and SimulationI wonder what MC34125 is, I don't know a gate driver IC of this type. As for the layout, the traces are surely sufficient for 3A, but using copper...5 replies | 189 view(s)
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17th March 2019, 09:59FvM replied to a thread Stability Simulation with Cadence in Analog Integrated Circuit (IC) Design, Layout and Fabricatione.g. a miller capacitor across CMFB amplifier transistor M3A.46 replies | 866 view(s)
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16th March 2019, 23:48FvM replied to a thread Stability Simulation with Cadence in Analog Integrated Circuit (IC) Design, Layout and FabricationFor a specific feedback topology, loop gain and closed loop gain are clearly related. In most feedback amplifier applications, closed loop behaviour...46 replies | 866 view(s)
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16th March 2019, 23:12O.K., apparently it's a problem of the ADC setup. Did you verify that the ADC is converting at all and showing reasonable status information?5 replies | 141 view(s)
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16th March 2019, 23:06FvM replied to a thread 3 phase 400Vac 5000W Full bridge converter power factor correction Buck or Boost type in Power ElectronicsYou are right, it's impossible to achieve sinusoidal input current through B6 bridge. But you can achieve 120° conduction angle with arbitrary...23 replies | 807 view(s)
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16th March 2019, 19:27That's not possible with the shown circuit, you need to measure the cable voltage drop separately. If you mean substracting a constant cable...9 replies | 268 view(s)
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16th March 2019, 13:54Do yo enable interrupts globally somewhere, e.g. by _IPL = 0 ?5 replies | 141 view(s)
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16th March 2019, 10:36FvM replied to a thread Stability Simulation with Cadence in Analog Integrated Circuit (IC) Design, Layout and FabricationIf you want to assess the CMFB loop stability, both test setups can be expected to have quite similar result.46 replies | 866 view(s)
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16th March 2019, 10:29The presented circuit topology (current source + differential amplifier) doesn't work for 3-wire. You need a special circuit that compensates for the...9 replies | 268 view(s)
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