2010vl04
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Today, 14:19I can't read a sense into sending the blood pressure signal to stimulation amplifier. What should be the purpose?4 replies | 70 view(s) -
Today, 14:12FvM replied to a thread Spartan6 (ISE 14.7) how to generate differential clock? in PLD, SPLD, GAL, CPLD, FPGA DesignThe inverted signal is generated in IO cell, the usual way is to have one output signal (e.g. a top level port of your design) and assign a...3 replies | 78 view(s)
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Today, 14:03FvM replied to a thread priority on two asynch triggered events in ASIC Design Methodologies and Tools (Digital)I checked with Quartus integrated synthesis, as expected the #7 code causes an error: The modified code according to post #10 can be compiled...12 replies | 624 view(s)
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Today, 11:49Looks like multiple problems at once. - changing CREG: either antenna or power supply problem - garbage characters: UART problems, defective modem...14 replies | 387 view(s)
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Today, 11:35FvM replied to a thread Spartan6 (ISE 14.7) how to generate differential clock? in PLD, SPLD, GAL, CPLD, FPGA DesignBy choosing a suitable differential output pin pair and the respective differential IO standard in constraint editor.3 replies | 78 view(s)
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Today, 11:25If you use low local data rate (e.g. 1.2K) and allow the modem to negotiate an "intelligent" protocol with error correction and data compression, no...13 replies | 940 view(s)
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Today, 10:56Firstly, I don't understand why the arbitrary design change (M14 gate connection) from post #22 to post #23 was made? Any problem of the old circuit...28 replies | 1794 view(s)
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Today, 10:42Current measurement can hardly act as a reliable fan operation monitor. Depending on the failure mode, the actual current may be any value between...28 replies | 1296 view(s)
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Today, 10:28Do you want to use the pressure transducer with its dedicated amplifier, or include the amplifier function in your design? In the latter case, does...4 replies | 70 view(s)
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Today, 10:09Before selecting suitable components and deciding about the layout, you need to fix the specification. impedance matching required for both...1 replies | 121 view(s)
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Today, 09:44FvM replied to a thread priority on two asynch triggered events in ASIC Design Methodologies and Tools (Digital)I guess there's a typo in post #7. This construct complies with the register template and should work in functional simulation as well: assign...12 replies | 624 view(s)
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Yesterday, 23:09FvM replied to a thread priority on two asynch triggered events in ASIC Design Methodologies and Tools (Digital)Your suggested construct doesn't comply with the synthesizable register template, I doubt that it will be accepted by synthesis tools. I don't yet...12 replies | 624 view(s)
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Yesterday, 11:42Current sense may be reduced down to 0.2 if you want maximal output current, efficiency will probably drop.11 replies | 398 view(s)
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Yesterday, 10:46FvM replied to a thread Help to make circuit for Nerve Stimulation Device in Hobby Circuits and Small Projects ProblemsThe "Amplipulse" designs gives at least an idea how a TENS instrument can be designed, the original DC current source approach is completely missing...24 replies | 5750 view(s)
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Yesterday, 10:25I think, the potential catastrophes are foreseeable and can be avoided if you clearly plan ahead the intended function. It's straightforward to have...4 replies | 278 view(s)
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Yesterday, 09:48180 ohm is the suggested value for 12V input and 1A Ipk. Read https://www.onsemi.com/pub/Collateral/AN920-D.PDF11 replies | 398 view(s)
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Yesterday, 09:33FvM replied to a thread Biasing Circuit for LNA with Chebyshev Bandpass Filter in Analog Circuit DesignThe circuit isn't the equivalent of post #1 which connects L2/C2 to a low impedance node, so not surprising to get different S11 and kill the...6 replies | 344 view(s)
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Yesterday, 09:24You should really read the documentation and understand what's appropriate according to the application and peer capabilities. Particularly I don't...13 replies | 940 view(s)
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20th April 2019, 23:14I guess the library SPDT switches are CMOS switches with respective drivers. If you want similar performance, there's no more simple circuit...3 replies | 211 view(s)
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20th April 2019, 23:01That's a badly designed circuit. 34063 needs a current limiting resistor at pin 8, refer to data sheets. Suggested dimensioning rule is Ic/Ib=20,...11 replies | 398 view(s)
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20th April 2019, 22:41FvM replied to a thread Conducted emissions: Noise current limit for house hold appliances. in Power ElectronicsI don't agree with your conclusions. Particularly they don't seem to be substantiated by detailed reading. Why do you think the CISPR 15 limit values...17 replies | 953 view(s)
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20th April 2019, 22:19According to the modem doc, everything can be set with AT+MS command. The command is in fact common to many 56k modems, e.g. the Elsa/Devolo modems I...13 replies | 940 view(s)
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20th April 2019, 22:01FvM replied to a thread Conducted emissions: Noise current limit for house hold appliances. in Power ElectronicsEven if there are no valid EMI regulations in your place (sure about?), people might expect compliance with common international standards like CISPR...17 replies | 953 view(s)
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20th April 2019, 12:55No that's wrong AT syntax and useless. Register commands are setting a specific register value. However, there's no standard register to set remote...13 replies | 940 view(s)
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20th April 2019, 12:46SPICE germanium transistor models are widely available, e.g. in the LTspice Yahoo forum. You can use it in any SPICE compatible simulator.1 replies | 202 view(s)
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20th April 2019, 12:25The experiment prerequisites aren't completely clear. Perhaps you should clarify in which situation you observe |S11| maxima and minima. If the...4 replies | 252 view(s)
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20th April 2019, 12:08Did you also consider to use an ADC evaluation board with FMC interface (e.g. AD9625 eval board) with a respective FPGA board. You can choose ADC and...1 replies | 125 view(s)
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20th April 2019, 12:01A reasonable method could be to let the modem select the protocol itself based on the peer capabilities and line quality. Otherwise you'll use the -...13 replies | 940 view(s)
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19th April 2019, 12:34FvM replied to a thread priority on two asynch triggered events in ASIC Design Methodologies and Tools (Digital)I agree with std_match, there's a potential simulation mismatch with this code, as discussed in previous Edaboard threads, e.g....12 replies | 624 view(s)
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19th April 2019, 12:03Errata sheets are displayed along with the product documentation at microchip.com. Typing "dspic30f4011 errata" at Google will probably answer...1 replies | 145 view(s)
About 2010vl04
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