barry
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15th February 2020, 21:56Boy, you didn’t even ATTEMPT to hide the fact that you’re asking us to do your homework. Take your F, and then go find another career.2 replies | 178 view(s)
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15th February 2020, 17:22Impedance is the reciprocal of transconductance.3 replies | 172 view(s)
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12th February 2020, 17:01First of all, I would highly recommend NOT trying to do USB for a first FPGA project. There's a LOT under the surface of USB. Unless you can find a...10 replies | 572 view(s)
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11th February 2020, 15:36Um, where’s the zener? This is making less and less sense. If you actually did have a zener in parallel with the LC, it would just conduct unlimited...6 replies | 264 view(s)
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11th February 2020, 07:23It’s not clear what you’re asking for. I have no idea what you mean by “an LC circuit with the reverse-biased...” could you maybe draw a schematic or...6 replies | 264 view(s)
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10th February 2020, 20:48barry replied to a thread Troubleshooting Circuit card in PCB Routing Schematic Layout software and SimulationVoltmeter. Oscilloscope. Logic analyzer. No software is going to be able to identify a hardware problem, particularly if you don't want to use JTAG.1 replies | 170 view(s)
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8th February 2020, 17:44barry replied to a thread Quartus error 12006 'undefined entity' in PLD, SPLD, GAL, CPLD, FPGA DesignSorry, Cyclone IV. See, I told you I was a Xilinx guy.6 replies | 401 view(s)
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8th February 2020, 01:55barry replied to a thread Quartus error 12006 'undefined entity' in PLD, SPLD, GAL, CPLD, FPGA DesignAha! Thanks. I'm a Xilinx guy. I searched a lot for any mention in the Intel docs, but didn't find much about clock buffers, but they did let me...6 replies | 401 view(s)
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7th February 2020, 22:50barry replied to a thread Quartus error 12006 'undefined entity' in PLD, SPLD, GAL, CPLD, FPGA DesignIt's a spartan 4. The buffer outputs go to the fabric, the inputs go to top level ports.6 replies | 401 view(s)
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7th February 2020, 18:57What is your input voltage? I think your inductor might be too small. Looking at the data sheet, they're using values of 170-220 uH. How did you...20 replies | 973 view(s)
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7th February 2020, 18:17I'm using Quartus Prime Lite and generated a clock buffer IP (using ALTIOBUF). It synthesizes fine in Synplify Pro, but when I try to compile the...6 replies | 401 view(s)
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3rd February 2020, 23:20Stupid assignment, IMO. You could just cascade several high gain rail-to-rail opamps, open-loop, connect the power supply to 3V, and VOILA!...6 replies | 690 view(s)
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3rd February 2020, 21:08Noise from the motors getting into your arduino? Software bug? You give us NOTHING to help you with.6 replies | 441 view(s)
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3rd February 2020, 05:18Please do a google search yourself. There are HUNDREDS of microcontrollers that have multiple ADCs. You don't give any other requirements. And you do...6 replies | 441 view(s)
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31st January 2020, 19:25Whaaaaaat? You give us absolutely NO information about your hardware or software, and then you ask us to give you ”code to read a microcontroller?” ...5 replies | 504 view(s)
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28th January 2020, 20:53ESD? Over-temperature?4 replies | 338 view(s)
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28th January 2020, 19:45barry replied to a thread [SOLVED] VHDL Simulation error using Xilinx ISE14.7 in PLD, SPLD, GAL, CPLD, FPGA DesignAnd that's why your simulation fails?15 replies | 863 view(s)
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28th January 2020, 18:51barry replied to a thread [SOLVED] VHDL Simulation error using Xilinx ISE14.7 in PLD, SPLD, GAL, CPLD, FPGA DesignVHDL does not have a data type of "word". Is this defined in your package, which you haven't shown us?15 replies | 863 view(s)
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26th January 2020, 07:08First of all, putting a diode from input to output will probably make the whole thing fail, and certainly won’t solve any problem. Why didn’t your...15 replies | 1988 view(s)
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24th January 2020, 22:12Do you mean VOLTAGE requirement? Or, do you really mean POWER? The voltage is specified by VCCO; it's in the data sheet. It depends on what your...5 replies | 583 view(s)
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23rd January 2020, 23:09Three votes for UART. If you're going to use a microcontroller, you might as well use a UART. It will be a lot more reliable.15 replies | 1988 view(s)
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23rd January 2020, 19:04So you have to continuously send a pulse train of 1ms /2ms etc. period to keep the speaker enabled? First of all, that's not PWM, that's simply a...15 replies | 1988 view(s)
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23rd January 2020, 17:15barry replied to a thread Configuring ICE40 FPGA directly from ESP32 uC rather than using dedicated flash IC in PLD, SPLD, GAL, CPLD, FPGA DesignYes, you can use the SPI ports for your own nefarious needs after configuration. Just pay attention to what's attached to those ports.7 replies | 490 view(s)
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23rd January 2020, 15:49If you design it properly, “it will work fine”. Long duration pulses? Low noise environment? But why PWM, Why not a single pulse of a specific...15 replies | 1988 view(s)
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23rd January 2020, 15:46barry replied to a thread GND For Connector Shielding in Professional Hardware and Electronics DesignYou’ve got three different grounds shown there, that’s a little confusing. Where do they all go? Where do the shield connections of each connector...5 replies | 531 view(s)
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23rd January 2020, 15:42barry replied to a thread Components nomenclature on PCB silkscreen in PCB Routing Schematic Layout software and SimulationI have never done this. Why do you think it’s important or useful to declare reference designators this way? When you look at the schematic,...2 replies | 362 view(s)
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23rd January 2020, 15:34barry replied to a thread Configuring ICE40 FPGA directly from ESP32 uC rather than using dedicated flash IC in PLD, SPLD, GAL, CPLD, FPGA Designim not familiar with your uc. Can you read data from program flash? If so, then you can use it to store your FPGA bitstream.7 replies | 490 view(s)
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