barry
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Today, 17:27RTFM. the reason you can’t get 3 amps is because your battery is incapable of producing 3 amps.4 replies | 20 view(s)
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Yesterday, 00:48barry replied to a thread Trying to get a pass in EMC in Professional Hardware and Electronics DesignUSA? India? UK? Jupiter? Help us out...2 replies | 217 view(s)
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25th February 2020, 22:18You could try your heat gun. You'll have to pay attention to surrounding components. Also, if there's a pad underneath the device, that will make it...3 replies | 197 view(s)
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25th February 2020, 01:40barry replied to a thread System Verilog error VLOG-13069 from Questasim with unpacked array in PLD, SPLD, GAL, CPLD, FPGA DesignWell, that was it; indices were reversed. My SV guru was adamant about doing it the (wrong) way that I was. Minus guru points for him. Thanks all.10 replies | 411 view(s)
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22nd February 2020, 01:29barry replied to a thread System Verilog error VLOG-13069 from Questasim with unpacked array in PLD, SPLD, GAL, CPLD, FPGA DesignThat’s the answer I was looking for; I simply had the indexes swapped. Someone who I thought knew more about such things misinformed me. I will try...10 replies | 411 view(s)
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21st February 2020, 23:09barry replied to a thread System Verilog error VLOG-13069 from Questasim with unpacked array in PLD, SPLD, GAL, CPLD, FPGA DesignNow youve REALLY confused me. Youve defined Bt1 as 8 elements of 4 bits each; youve shown it as an array of 8 elements of 32 bits. But still,...10 replies | 411 view(s)
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21st February 2020, 17:04barry replied to a thread System Verilog error VLOG-13069 from Questasim with unpacked array in PLD, SPLD, GAL, CPLD, FPGA DesignFirst of all, I don’t think that’s right. Second of all, I shouldn’t have gotten that error even if the dimensions were reversed, i.e., the...10 replies | 411 view(s)
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21st February 2020, 01:39barry started a thread System Verilog error VLOG-13069 from Questasim with unpacked array in PLD, SPLD, GAL, CPLD, FPGA DesignI've finally bitten the bullet and crossed over from VHDL to the dark world of System Verilog. I've got a testbench that causes Questasim (Modelsim)...10 replies | 411 view(s)
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20th February 2020, 23:02barry replied to a thread How to get the operating temperature ( case temperature) in Thermal ManagementRight there, on page 3, is Tjc, junction-to-case thermal resistance (only for the SOIC, however. Not sure why they left that parameter off for the...3 replies | 340 view(s)
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20th February 2020, 19:02barry replied to a thread [moved] External Ethernet Microcontroller or ZYNQ in PLD, SPLD, GAL, CPLD, FPGA DesignZYNQ IS an FPGA. There are cores that implement 1G MAC in an FPGA, and chips that do it externally. Both methods meet the requirements of 1Gig...5 replies | 377 view(s)
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15th February 2020, 21:56Boy, you didn’t even ATTEMPT to hide the fact that you’re asking us to do your homework. Take your F, and then go find another career.2 replies | 264 view(s)
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15th February 2020, 17:22Impedance is the reciprocal of transconductance.3 replies | 277 view(s)
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12th February 2020, 17:01First of all, I would highly recommend NOT trying to do USB for a first FPGA project. There's a LOT under the surface of USB. Unless you can find a...10 replies | 736 view(s)
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11th February 2020, 15:36Um, where’s the zener? This is making less and less sense. If you actually did have a zener in parallel with the LC, it would just conduct unlimited...6 replies | 346 view(s)
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11th February 2020, 07:23It’s not clear what you’re asking for. I have no idea what you mean by “an LC circuit with the reverse-biased...” could you maybe draw a schematic or...6 replies | 346 view(s)
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10th February 2020, 20:48barry replied to a thread Troubleshooting Circuit card in PCB Routing Schematic Layout software and SimulationVoltmeter. Oscilloscope. Logic analyzer. No software is going to be able to identify a hardware problem, particularly if you don't want to use JTAG.1 replies | 223 view(s)
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8th February 2020, 17:44barry replied to a thread Quartus error 12006 'undefined entity' in PLD, SPLD, GAL, CPLD, FPGA DesignSorry, Cyclone IV. See, I told you I was a Xilinx guy.6 replies | 524 view(s)
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8th February 2020, 01:55barry replied to a thread Quartus error 12006 'undefined entity' in PLD, SPLD, GAL, CPLD, FPGA DesignAha! Thanks. I'm a Xilinx guy. I searched a lot for any mention in the Intel docs, but didn't find much about clock buffers, but they did let me...6 replies | 524 view(s)
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7th February 2020, 22:50barry replied to a thread Quartus error 12006 'undefined entity' in PLD, SPLD, GAL, CPLD, FPGA DesignIt's a spartan 4. The buffer outputs go to the fabric, the inputs go to top level ports.6 replies | 524 view(s)
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7th February 2020, 18:57What is your input voltage? I think your inductor might be too small. Looking at the data sheet, they're using values of 170-220 uH. How did you...20 replies | 1179 view(s)
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7th February 2020, 18:17I'm using Quartus Prime Lite and generated a clock buffer IP (using ALTIOBUF). It synthesizes fine in Synplify Pro, but when I try to compile the...6 replies | 524 view(s)
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3rd February 2020, 23:20Stupid assignment, IMO. You could just cascade several high gain rail-to-rail opamps, open-loop, connect the power supply to 3V, and VOILA!...6 replies | 796 view(s)
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3rd February 2020, 21:08Noise from the motors getting into your arduino? Software bug? You give us NOTHING to help you with.6 replies | 567 view(s)
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3rd February 2020, 05:18Please do a google search yourself. There are HUNDREDS of microcontrollers that have multiple ADCs. You don't give any other requirements. And you do...6 replies | 567 view(s)
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31st January 2020, 19:25Whaaaaaat? You give us absolutely NO information about your hardware or software, and then you ask us to give you ”code to read a microcontroller?” ...5 replies | 600 view(s)
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