barry
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Yesterday, 17:01barry replied to a thread Detect the absence of sampled AC signal (from digital filter) in verilog in PLD, SPLD, GAL, CPLD, FPGA DesignIf your signal has enough amplitude I would think that using the level detection method should be the easiest; noise shouldn't be an issue. What is...5 replies | 296 view(s)
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Yesterday, 16:55How are you testing this? How are you applying a "2KV surge"? How are you measuring it? What are its characteristics? Are you picking up something...5 replies | 118 view(s)
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10th October 2019, 20:51Read post #3 again. adsff explains how to use the digital elements of an FPGA to effect analog functions. But you can't "write program for analog...8 replies | 556 view(s)
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10th October 2019, 15:27You need more than Verilog code, you need analog circuitry to implement an ADC: comparators or opamps, etc. Unless your FPGA has those features,...8 replies | 556 view(s)
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10th October 2019, 00:03barry replied to a thread What is the vhdl equivalent of "initial begin" to initialize a ROM. in PLD, SPLD, GAL, CPLD, FPGA DesignI don’t see how the example in #9 can load the ROM from the bit file; it uses a clock.14 replies | 554 view(s)
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9th October 2019, 21:34barry replied to a thread What is the vhdl equivalent of "initial begin" to initialize a ROM. in PLD, SPLD, GAL, CPLD, FPGA DesignI don't understand what you've got there. What is "rom_op" ? What is addr? Isn't that logic? How do you get data into a RAM without writing it? (To...14 replies | 554 view(s)
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9th October 2019, 18:44barry replied to a thread Film capacitor failed in flyback smps at high temperature? in Power ElectronicsIf you read the data sheet, you'll see that the operating frequency of the cap has a large impact on it. What's your frequency? What's your 'extreme'...5 replies | 427 view(s)
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9th October 2019, 18:39barry replied to a thread Instrumentation AMP Virtual short. in Hobby Circuits and Small Projects ProblemsYes, it's a virtual short. If you actually analyze the circuit, you'll see that as the IA open-loop gain goes to infinity, the voltage at the two...5 replies | 653 view(s)
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9th October 2019, 18:36barry replied to a thread Why are SMD components so much smaller than their THT versions? in Analog Circuit DesignThe die is the EXACT SAME SIZE for through-hole or SMT devices. The TH parts are bigger in order to acommodate the larger lead frame. You'll notice...3 replies | 266 view(s)
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9th October 2019, 18:33barry replied to a thread What is the vhdl equivalent of "initial begin" to initialize a ROM. in PLD, SPLD, GAL, CPLD, FPGA DesignMaybe just a minor point (depending on speed and utilization), but when it's implemented in the code, you now have to generate all the associated...14 replies | 554 view(s)
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9th October 2019, 16:20barry replied to a thread What is the vhdl equivalent of "initial begin" to initialize a ROM. in PLD, SPLD, GAL, CPLD, FPGA DesignIf it's a ROM, can't you just define it as an IP block that gets loaded during configuration? For example, with the Xilinx tools you would have a...14 replies | 554 view(s)
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4th October 2019, 15:23I can spot the mistake: those protoboards are TERRIBLE for the type of circuit you are playing with. Stray inductance, stray capacitance, etc....19 replies | 818 view(s)
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2nd October 2019, 16:39barry replied to a thread Data string length to be send out from FPGA in PLD, SPLD, GAL, CPLD, FPGA Design1) Receive command "Read All"==>transmit all the data 2) Receive command "Read Register X"==>transmit the data in Register X I really don't...4 replies | 290 view(s)
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1st October 2019, 20:48barry replied to a thread Altium "has only one pin" error - why? in Software Problems, Hints and ReviewsYou didn't split your bus out correctly. Look at this-"creating a Multichannel design":...5 replies | 1042 view(s)
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1st October 2019, 19:13barry replied to a thread Altium "has only one pin" error - why? in Software Problems, Hints and ReviewsOn the top level AOUTR is a bus. On your schematic, it's a single signal.5 replies | 1042 view(s)
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1st October 2019, 17:59barry replied to a thread Altium "has only one pin" error - why? in Software Problems, Hints and ReviewsWithout seeing the underlying schematic, audioinput.schdoc, it's impossible to tell.5 replies | 1042 view(s)
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30th September 2019, 16:51barry replied to a thread Determine whether a binary number is of power of two in verilog code in PLD, SPLD, GAL, CPLD, FPGA DesignI told you it was early in the morning!14 replies | 657 view(s)
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30th September 2019, 15:38barry replied to a thread Determine whether a binary number is of power of two in verilog code in PLD, SPLD, GAL, CPLD, FPGA DesignWithout thinking too hard early on a Monday morning, I think this could be done with a bunch of cascaded XORs. Output would be logic 1 if only one...14 replies | 657 view(s)
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30th September 2019, 05:43barry replied to a thread Is a tantulum different from a microfarad tantulum cap? in Analog Circuit DesignI think you misheard. MICROFARAD, not “microferret”. And, there’s no such thing as a .68k cap. .68 microfarad, maybe? 68 microfarad?9 replies | 445 view(s)
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29th September 2019, 21:27barry replied to a thread Help!! with MUX and Shift Registers in an architecture in PLD, SPLD, GAL, CPLD, FPGA DesignEXTREMELY unclear. 16 64-bit registers? You seem to only show 15 registers. What is “equation (I)”? I don’t see that on your drawing. What is BSIZE?...3 replies | 252 view(s)
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29th September 2019, 16:40What a mess!! First of all, you’re going to draw over 50mA from V2 when it’s high, exceeding its limit. And, again, why would you expect an LED...3 replies | 303 view(s)
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28th September 2019, 17:12What are you talking about? Charging? What charging? All I see is two voltage sources. Your red LED has no current limiting resistor. It is...3 replies | 303 view(s)
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28th September 2019, 16:571) A schematic with no resistor values is kind of useless. It’s also incomplete. Where do the JTAG signals go? 2) Have you looked at signals with a...10 replies | 477 view(s)
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27th September 2019, 21:45barry replied to a thread Why would a scope suddenly give noisy traces when it never used to? in Elementary Electronic QuestionsIs the noise there with the scope tip grounded or connected to the scope calibration signal?6 replies | 376 view(s)
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27th September 2019, 21:43It’s not just the inductance, it’s also the current rating, as mentioned. But I’m betting on the problem being the power supply being overloaded.19 replies | 818 view(s)
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25th September 2019, 17:23barry replied to a thread Need to remove the FFC Connector..Help me.. in Professional Hardware and Electronics DesignThe only problem I could foresee would be if there is excessive shock the Berg strip/pcb connection could fracture, whereas the flat cable gives more...1 replies | 279 view(s)
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25th September 2019, 17:18barry replied to a thread [SOLVED] Looking for Connector Type? in Service Manuals, Requests, Repair TipsIt could be a Molex type. It could be an AMP type. Without any dimensions it's pointless to even guess.3 replies | 441 view(s)
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25th September 2019, 06:38You need to learn about thermal conductivity. We can’t give you an entire course, but you can ask specific questions.10 replies | 1238 view(s)
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25th September 2019, 04:02Read the data sheet. It can dissipate 200w with a case temperature of 25 deg, not AMBIENT of 25 deg.10 replies | 1238 view(s)
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25th September 2019, 03:21barry replied to a thread [SOLVED] Shift register implementation and use of its value in PLD, SPLD, GAL, CPLD, FPGA DesignImpossible. This is not a shift register no matter what you think your simulation is showing.22 replies | 809 view(s)
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