barry
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Today, 17:05RX of device to TX of MCU and TX of device to RX of MCU. I'm not really sure I understand your question.3 replies | 88 view(s)
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Today, 15:39It depends on what you want your design to do. WE sure don't know. RTS and CTS are handshaking signals. Maybe you need them. Maybe you don't. Are...3 replies | 88 view(s)
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Yesterday, 15:34barry replied to a thread Rigid flex Cross section OrCAD PCB Designer in PCB Routing Schematic Layout software and SimulationMaybe, just maybe, you should tell us what software you are using. Showing a picture of the dialog for selecting layer colors is useless. Maybe you...9 replies | 663 view(s)
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21st October 2019, 19:21Why do you say: "The 820 of course tells me the value of the res"? Maybe the 820 tells you reference designator and 1K is actually the value. Maybe...3 replies | 159 view(s)
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20th October 2019, 15:45barry replied to a thread Usage of Synchronous and Asynchronuos FIFOs in ASIC Design Methodologies and Tools (Digital)It’s not just the clock speed that’s important. Are the clocks SYNCHRONOUS or ASYNCHRONOUS to each other? Asynchronous FIFOs are more complex.2 replies | 244 view(s)
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18th October 2019, 20:52That seems correct.6 replies | 386 view(s)
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17th October 2019, 15:40barry replied to a thread [SOLVED] Generation of 4 Phase Shifted clock Signals in Analog Circuit DesignWhat kind of system would you have that requires a clock, but doesn't want to use digital logic?12 replies | 650 view(s)
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15th October 2019, 17:20barry replied to a thread [SOLVED] Generation of 4 Phase Shifted clock Signals in Analog Circuit DesignUse an FPGA. Use a microprocessor. Use some resistors, capacitors and inductors. Perhaps if you asked a better question you would get a better...12 replies | 650 view(s)
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14th October 2019, 17:01barry replied to a thread Detect the absence of sampled AC signal (from digital filter) in verilog in PLD, SPLD, GAL, CPLD, FPGA DesignIf your signal has enough amplitude I would think that using the level detection method should be the easiest; noise shouldn't be an issue. What is...6 replies | 500 view(s)
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14th October 2019, 16:55How are you testing this? How are you applying a "2KV surge"? How are you measuring it? What are its characteristics? Are you picking up something...6 replies | 284 view(s)
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10th October 2019, 20:51Read post #3 again. adsff explains how to use the digital elements of an FPGA to effect analog functions. But you can't "write program for analog...8 replies | 719 view(s)
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10th October 2019, 15:27You need more than Verilog code, you need analog circuitry to implement an ADC: comparators or opamps, etc. Unless your FPGA has those features,...8 replies | 719 view(s)
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10th October 2019, 00:03barry replied to a thread What is the vhdl equivalent of "initial begin" to initialize a ROM. in PLD, SPLD, GAL, CPLD, FPGA DesignI don’t see how the example in #9 can load the ROM from the bit file; it uses a clock.14 replies | 750 view(s)
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9th October 2019, 21:34barry replied to a thread What is the vhdl equivalent of "initial begin" to initialize a ROM. in PLD, SPLD, GAL, CPLD, FPGA DesignI don't understand what you've got there. What is "rom_op" ? What is addr? Isn't that logic? How do you get data into a RAM without writing it? (To...14 replies | 750 view(s)
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9th October 2019, 18:44barry replied to a thread Film capacitor failed in flyback smps at high temperature? in Power ElectronicsIf you read the data sheet, you'll see that the operating frequency of the cap has a large impact on it. What's your frequency? What's your 'extreme'...5 replies | 521 view(s)
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9th October 2019, 18:39barry replied to a thread Instrumentation AMP Virtual short. in Hobby Circuits and Small Projects ProblemsYes, it's a virtual short. If you actually analyze the circuit, you'll see that as the IA open-loop gain goes to infinity, the voltage at the two...5 replies | 776 view(s)
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9th October 2019, 18:36barry replied to a thread Why are SMD components so much smaller than their THT versions? in Analog Circuit DesignThe die is the EXACT SAME SIZE for through-hole or SMT devices. The TH parts are bigger in order to acommodate the larger lead frame. You'll notice...3 replies | 347 view(s)
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9th October 2019, 18:33barry replied to a thread What is the vhdl equivalent of "initial begin" to initialize a ROM. in PLD, SPLD, GAL, CPLD, FPGA DesignMaybe just a minor point (depending on speed and utilization), but when it's implemented in the code, you now have to generate all the associated...14 replies | 750 view(s)
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9th October 2019, 16:20barry replied to a thread What is the vhdl equivalent of "initial begin" to initialize a ROM. in PLD, SPLD, GAL, CPLD, FPGA DesignIf it's a ROM, can't you just define it as an IP block that gets loaded during configuration? For example, with the Xilinx tools you would have a...14 replies | 750 view(s)
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4th October 2019, 15:23I can spot the mistake: those protoboards are TERRIBLE for the type of circuit you are playing with. Stray inductance, stray capacitance, etc....19 replies | 973 view(s)
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2nd October 2019, 16:39barry replied to a thread Data string length to be send out from FPGA in PLD, SPLD, GAL, CPLD, FPGA Design1) Receive command "Read All"==>transmit all the data 2) Receive command "Read Register X"==>transmit the data in Register X I really don't...4 replies | 365 view(s)
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1st October 2019, 20:48barry replied to a thread Altium "has only one pin" error - why? in Software Problems, Hints and ReviewsYou didn't split your bus out correctly. Look at this-"creating a Multichannel design":...5 replies | 1139 view(s)
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1st October 2019, 19:13barry replied to a thread Altium "has only one pin" error - why? in Software Problems, Hints and ReviewsOn the top level AOUTR is a bus. On your schematic, it's a single signal.5 replies | 1139 view(s)
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1st October 2019, 17:59barry replied to a thread Altium "has only one pin" error - why? in Software Problems, Hints and ReviewsWithout seeing the underlying schematic, audioinput.schdoc, it's impossible to tell.5 replies | 1139 view(s)
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30th September 2019, 16:51barry replied to a thread Determine whether a binary number is of power of two in verilog code in PLD, SPLD, GAL, CPLD, FPGA DesignI told you it was early in the morning!14 replies | 807 view(s)
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30th September 2019, 15:38barry replied to a thread Determine whether a binary number is of power of two in verilog code in PLD, SPLD, GAL, CPLD, FPGA DesignWithout thinking too hard early on a Monday morning, I think this could be done with a bunch of cascaded XORs. Output would be logic 1 if only one...14 replies | 807 view(s)
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30th September 2019, 05:43barry replied to a thread Is a tantulum different from a microfarad tantulum cap? in Analog Circuit DesignI think you misheard. MICROFARAD, not “microferret”. And, there’s no such thing as a .68k cap. .68 microfarad, maybe? 68 microfarad?9 replies | 549 view(s)
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29th September 2019, 21:27barry replied to a thread Help!! with MUX and Shift Registers in an architecture in PLD, SPLD, GAL, CPLD, FPGA DesignEXTREMELY unclear. 16 64-bit registers? You seem to only show 15 registers. What is “equation (I)”? I don’t see that on your drawing. What is BSIZE?...3 replies | 304 view(s)
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29th September 2019, 16:40What a mess!! First of all, you’re going to draw over 50mA from V2 when it’s high, exceeding its limit. And, again, why would you expect an LED...3 replies | 335 view(s)
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28th September 2019, 17:12What are you talking about? Charging? What charging? All I see is two voltage sources. Your red LED has no current limiting resistor. It is...3 replies | 335 view(s)
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