std_match
Advanced Member level 3
Find latest posts
View Articles
View Blog EntriesMini Statistics
- Join Date
- 9th July 2010
- Last Activity
- Yesterday 18:18
- Blog Entries
- 0
More 3 Friends
Awards
No Awards.
Achievements
7 years registeredRecent Visitors
- ads-ee,
- andre_teprom,
- betwixt,
- biastee,
- kahroba92,
- KlausST,
- nicklas_a74,
- pancho_hideboo,
- SvM4,
- weetabixharry
- Tab Content
- std_match's Activity
- About Me
- Friends
- Experience
-
Older Activity
-
Yesterday, 18:16std_match replied to a thread To which standards must we conform for our electronics/electrical product? in Professional Hardware and Electronics DesignStart a discussion with a certified EMC lab. They should be able to tell you what EMC-related standards you should follow for different markets....4 replies | 182 view(s) -
12th September 2019, 09:07std_match replied to a thread Using calculated CRC as seed for the next CRC calculation in PLD, SPLD, GAL, CPLD, FPGA DesignYou should just feed more data into the crc module. Apply the new data and crc_en='1' for one clock cycle. Do you really need to process 256...4 replies | 238 view(s)
-
11th September 2019, 09:56std_match replied to a thread Implementation of a MUX for selecting from 2 different sets of inputs in PLD, SPLD, GAL, CPLD, FPGA DesignAt the lowest level there will be one MUX per output bit, so there is not much to optimize.5 replies | 208 view(s)
-
11th September 2019, 09:52std_match replied to a thread Unable to run the simulation correctly ( Modelsim ) in PLD, SPLD, GAL, CPLD, FPGA DesignIn pulse_detector, you assign values to event_pcounter in two different always blocks. When they assign different values you get the 'x' in...2 replies | 140 view(s)
-
4th September 2019, 08:27Try to declare the component prototype of "Reset_Delay" in the .VHD file where you instantiate it - instead of instantiating it from work.reset_delay.2 replies | 258 view(s)
-
4th September 2019, 08:20shaiko replied to a thread Inferred VHDL dual port RAM template in PLD, SPLD, GAL, CPLD, FPGA DesignHi, It'll be easier to understand what you're proposing if you post a code example.7 replies | 475 view(s)
-
3rd September 2019, 13:26std_match replied to a thread pcie hard ip altera- latency problem in PLD, SPLD, GAL, CPLD, FPGA DesignThe latency can vary a lot in the real world, and it seems normal in your case. I think your state machine should be able to handle latencies up to...3 replies | 368 view(s)
-
30th August 2019, 09:05shaiko replied to a thread Inferred VHDL dual port RAM template in PLD, SPLD, GAL, CPLD, FPGA DesignWhen was the last time you tried it ? They do have a template that makes use of a shared variable - but it's for a "True Dual-Port RAM with a...7 replies | 475 view(s)
-
30th August 2019, 00:01Hello, Taken from this link:...7 replies | 475 view(s)
-
27th August 2019, 10:40Don't use % values. Eq 1 D = 1 - (8 * 0.7 / 25) = 0.776 Eq 2 ΔIL = (8 * 0.776) / (1.2M * 6.8u) = 0.76A Eq 3 Imax-out = (4 - 0.76/2) * (1 -...24 replies | 1100 view(s)
-
26th August 2019, 23:54The top level test bench should focus on connectivity. All wires/signals between the modules must be verified, but the possible values/combinations...6 replies | 561 view(s)
-
23rd August 2019, 16:27std_match replied to a thread HP 54520A Blown Fuse Problem in Service Manuals, Requests, Repair TipsTry to connect an old-fashioned light bulb instead of the fuse. If you are lucky the light bulb will stay off until the problem happens, and it will...32 replies | 1498 view(s)
-
23rd August 2019, 10:27std_match replied to a thread [SOLVED] bjt safe operating area diagram in Elementary Electronic QuestionsIt is a typo. The upper one should be 1.02 replies | 212 view(s)
-
22nd August 2019, 14:43std_match replied to a thread Lattice FPGAs and Diamond software in PLD, SPLD, GAL, CPLD, FPGA DesignTHe ECP5 family can be clocked above 200 MHz for the logic. For the I/O you can have at least 400 MHz DDR = 800 Mbit/s per pin. The Diamond...5 replies | 542 view(s)
-
22nd August 2019, 01:47std_match replied to a thread P mosfet turns on/voltage at drain during powerup in Elementary Electronic QuestionsRemove C139. You should not have a capacitor between gate and drain. When you press the button, C136 and C139 form a capacitive voltage divider that...5 replies | 405 view(s)
-
16th August 2019, 10:10Do you have any load on the +12V output? With no load, overshoots and ringings can be rectified by the diode and increase the output voltage.18 replies | 876 view(s)
About std_match
Basic Information
Optional Info
- Location:
- Sweden
Statistics
Total Posts
- Total Posts
- 961
- Posts Per Day
- 0.29
General Information
- Last Activity
- Yesterday 18:18
- Join Date
- 9th July 2010
Helpful Postings
- Has Rated
- 23
- Post Rated
- Rated helpful 373 out of 373 times
3 Friends
Showing Friends 1 to 3 of 3
Experience
Points
- Points
- 7,259
- Level
- 20
Level up completed
- Level up completed
- 30%
- Points required
- 491
Activity
- Activity
- 24.0%
- Activity last 30 days
- 36.0%
- Activity last 7 days
- 39.0%
Points
All Points for user
- Points for User
- 2,431
- Points for Reputation
- 745
- Points for every day since registration
- 1,677
- Points for Friends
- 9
All Points for threads
- Points for threads
- 103
- Points for Threads
- 10
- Points for tagging threads
- 84
- Points for replies
- 8
All Points for posts
- Points for Posts
- 4,725
- Points for Posts
- 2,862
- Helpful Answers
- 1,860
- Solved Threads
- 3
All Points for miscellaneous
- Points for Misc
- 0
Activities
15th September 2019
- 03:06 std_match has earned 1 Points for User points
13th September 2019
- 03:06 std_match has earned 3 Points for Posts points
- 03:06 std_match has earned 1 Points for User points
12th September 2019
- 03:06 std_match has earned 6 Points for Posts points
- 03:06 std_match has earned 2 Points for User points
7th September 2019
- 03:06 std_match has earned 2 Points for User points
4th September 2019
- 03:06 std_match has earned 3 Points for Posts points
3rd September 2019
- 03:06 std_match has earned 2 Points for User points
30th August 2019
- 03:06 std_match has earned 1 Points for User points
28th August 2019
- 03:06 std_match has earned 8 Points for Posts points
- 03:06 std_match has earned 3 Points for User points
27th August 2019
- 03:06 std_match has earned 8 Points for Posts points
- 03:06 std_match has earned 3 Points for User points
24th August 2019
- 03:06 std_match has earned 6 Points for Posts points
- 03:06 std_match has earned 1 Points for User points
23rd August 2019
- 03:06 std_match has earned 8 Points for Posts points
- 03:06 std_match has earned 2 Points for User points
- 03:06 std_match has earned 1 Points for threads points
22nd August 2019
- 03:07 std_match has earned 3 Points for Posts points
- 03:07 std_match has earned 1 Points for User points
Show Activities from all Users