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std_match
std_match
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Yesterday,
12:21
std_match
replied to a thread
0-100uA analogue meter (needle) to show 0-10v
in
Analog Circuit Design
The series resistor should be less than 100k. You must subtract the meter's internal resistance from the theoretical 100k value (10V/100uA). In...
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6 replies | 153 view(s)
10th December 2019,
10:01
std_match
replied to a thread
Bilinear switched capacitor resistor equivalent resistance
in
Analog Circuit Design
Charge is transferred to the output also when s1 is closed. What you describe happens 2 times per clock cycle.
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4 replies | 300 view(s)
8th December 2019,
01:36
shaiko
replied to a thread
Error while trying to compile a header file in Xilinx SDK
in
Microcontrollers
Hi, The part is Zynq 7000. I think the compiler is GCC - but I'm not sure (a screenshot is attached).
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2 replies | 214 view(s)
8th December 2019,
00:27
shaiko
started a thread
Error while trying to compile a header file in Xilinx SDK
in
Microcontrollers
Hello, I'm trying to compile a project inside Xilinx's SDK (which is Eclipse based). I get the following error: no matches converting function...
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2 replies | 214 view(s)
3rd December 2019,
16:06
std_match
replied to a thread
Latchup Caused by diodes
in
Analog Integrated Circuit (IC) Design, Layout and Fabrication
A thyristor can be modelled as two transistors that keep each other saturated. This can't happen if you replace one of the transistors with a diode....
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2 replies | 249 view(s)
3rd December 2019,
10:13
std_match
replied to a thread
Flyback controller explain
in
Power Electronics
The output voltage will probably be wrong, and it will change when the input voltage changes. You can check with a scope that the diodes on the...
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23 replies | 1171 view(s)
2nd December 2019,
16:08
std_match
replied to a thread
[PIC] MikroC for PIC32 PIC32MZ MCU Clock Frquency [MHz] bug?
in
Microcontrollers
Look in the compiler manual. Some delay functions are based on the "oscillator frequency" and some other delay functions are based on the "MCU...
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3 replies | 422 view(s)
22nd November 2019,
13:57
std_match
replied to a thread
2:1 Multiplexer with open drain Outputs IC
in
Analog Circuit Design
I think it would be better to use a MUX on the signal going to the TDO pin on the connector. If you need to disconnect the ASIC TDI pin when the...
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14 replies | 770 view(s)
20th November 2019,
14:51
std_match
replied to a thread
2:1 Multiplexer with open drain Outputs IC
in
Analog Circuit Design
The original request can be solved with a single 74HC4066 and 4 resistors: The unmarked resistors should not be critikal. Use 10K or whatever....
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14 replies | 770 view(s)
20th November 2019,
11:49
std_match
replied to a thread [SOLVED]
fixed point arithmetic in c
in
Microcontrollers
The two's complement format is good for addition/subtraction, but bad for multiplication/division. You want to multiply Q1.15 values 23166 (0.707)...
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16 replies | 1043 view(s)
20th November 2019,
00:08
shaiko
replied to a thread
Assigning a null array in VHDL
in
PLD, SPLD, GAL, CPLD, FPGA Design
TrickyDicky, The solution with the constant worked. But what if x was an array of integers ? type array_1d_integer is array ( integer range <> )...
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7 replies | 541 view(s)
19th November 2019,
16:49
shaiko
replied to a thread
Assigning a null array in VHDL
in
PLD, SPLD, GAL, CPLD, FPGA Design
Sorry. I viewed this on my cellphone first. And what you wrote in the line of code didn't show. Forum admins - please note of this problem. A...
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7 replies | 541 view(s)
19th November 2019,
14:33
shaiko
replied to a thread
Assigning a null array in VHDL
in
PLD, SPLD, GAL, CPLD, FPGA Design
This is what I tried to do. But how will the definition of that constant look? Please show an example.
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7 replies | 541 view(s)
19th November 2019,
14:17
shaiko
started a thread
Assigning a null array in VHDL
in
PLD, SPLD, GAL, CPLD, FPGA Design
Hello, In a package I have the following definition of a unconstrained unsigned array: type array_1d_unsigned is array ( integer range <> ) of...
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7 replies | 541 view(s)
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