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• 31st March 2020, 16:42
90 dB = 20 * log(voltage_ratio) => voltage_ratio = 10^(90/20) = 31623 The output will change max 1/31623 of the input common mode change. In...
3 replies | 229 view(s)
• 30th March 2020, 08:33
Watch the ESD bag/mat videos by Dave Jones: https://www.youtube.com/watch?v=imdtXcnywb8 EEVblog #247 - Anti Static Bag Myth Revisted...
17 replies | 739 view(s)
• 26th March 2020, 15:27
Maybe you told Vivado that it's a VHDL file?
13 replies | 748 view(s)
• 24th March 2020, 10:05
The TC output is wrong, should be '1' when the counter is "1111" and CET = '1'. The parallel load is wrong, should happen when PE = '0', regardless...
7 replies | 480 view(s)
• 20th March 2020, 14:21
The clock input is inverted on the lower left DFF (DFF3). Three samples are used, taken with a half clock cycle interval between the samples. With...
11 replies | 618 view(s)
• 18th March 2020, 18:04
My guess: The mixer W0 is of the switching/sampling type, which means that the switch in W0 is operated at the LO frequency with a 50% duty cycle....
2 replies | 363 view(s)
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