erikl -

Today, 21:42

pragash replied to a thread Problem with Keysight ADS EM simulation in Electromagnetic Design and Simulation

Dear Volker, question: Do you have an infinite bottom ground in your stackup that is used for all port ground references? answer: no, I don't. ...

4 replies | 174 view(s)

Today, 18:18

pragash replied to a thread Problem with Keysight ADS EM simulation in Electromagnetic Design and Simulation

Dear Volker, Above problem solved. thank you. I got a new problem now. During EM simulation i got this warning message. "Port 1 does not...

4 replies | 174 view(s)

Yesterday, 02:58

pragash started a thread Problem with Keysight ADS EM simulation in Electromagnetic Design and Simulation

hi all, im not able to view my layout which has been imported from Altium via ODB++ format! when i click "3D EM preview", below error appears. ...

4 replies | 174 view(s)

22nd June 2018, 16:21

Dominik Przyborowski replied to a thread Folded cascode OTA design in Analog Integrated Circuit (IC) Design, Layout and Fabrication

*.scs are the Spectre® model files in PDK's main directory should be a 'doc' directory with tones of pdf files consisting tutorials, manuals, model...

11 replies | 355 view(s)

22nd June 2018, 06:28

Dominik Przyborowski replied to a thread Folded cascode OTA design in Analog Integrated Circuit (IC) Design, Layout and Fabrication

Threshold voltage is a non-physical parameter so you should not worry about it, but base all necessary calculations on inversion coefficient. About...

11 replies | 355 view(s)

21st June 2018, 19:07

Dominik Przyborowski replied to a thread Folded cascode OTA design in Analog Integrated Circuit (IC) Design, Layout and Fabrication

For this FDSOI technology back-gate default connection is ground for all core devices (however for thick oxide ones not). @Shishira: How do you...

11 replies | 355 view(s)

20th June 2018, 03:39

shanmei replied to a thread extract the dc current in Analog Integrated Circuit (IC) Design, Layout and Fabrication

The ac range is around 1MHz- 500MHz signal, maximum value is 20mA. DC signal maximum value is also 20mA range. Thanks.

4 replies | 128 view(s)

20th June 2018, 01:10

shanmei started a thread extract the dc current in Analog Integrated Circuit (IC) Design, Layout and Fabrication

The input current contains both ac and dc signal, how can I extract dc current, and only have ac current? Thanks.

4 replies | 128 view(s)

18th June 2018, 08:30

LvW replied to a thread gyroscopes and LP filter in Analog Circuit Design

Yes - I could not find any mentioning of -90 deg....

17 replies | 323 view(s)

16th June 2018, 09:27

LvW replied to a thread Loop-gain calculation in Analog Circuit Design

Just a short comment: Each active device exhibits a typical roll-off chracteristics for higher frequencies. This is a general rule ...and nobody...

26 replies | 707 view(s)

15th June 2018, 23:21

erikl replied to a thread [moved] Conventional well device and flipped well device in Analog Integrated Circuit (IC) Design, Layout and Fabrication

Please check this presentation. At the bottom of this presentation, read The FBB advantage.

5 replies | 398 view(s)

15th June 2018, 22:50

erikl replied to a thread NMOS and PMOS W/L Ratio in Analog Integrated Circuit (IC) Design, Layout and Fabrication

W/L ratio doesn't depend on process size, it depends on the circuit and its application.

2 replies | 162 view(s)

15th June 2018, 10:42

LvW replied to a thread Loop-gain calculation in Analog Circuit Design

If you would read again the contributions in post#5 and post#19 you will see that - of course - R1 is part of the feedback loop. Remember the...

26 replies | 707 view(s)

14th June 2018, 17:05

LvW replied to a thread Loop-gain calculation in Analog Circuit Design

What is an "actual input"? What is your definition? The CMOS inverter has only one single input node - the common node for both gates. Is there any...

26 replies | 707 view(s)

14th June 2018, 12:30

hetang0503 started a thread NMOS and PMOS W/L Ratio in Analog Integrated Circuit (IC) Design, Layout and Fabrication

Hello, I am working on the chip level design using the GF 22FDSOI 20nm technology. In 20nm technology how to set W/L ratio.

2 replies | 162 view(s)

14th June 2018, 09:54

LvW replied to a thread Loop-gain calculation in Analog Circuit Design

The two transistors can be used as a linear amplifier. The same applies to an opamp. However, the problem in both cases is that - without negative...

26 replies | 707 view(s)

13th June 2018, 13:56

LvW replied to a thread Loop-gain calculation in Analog Circuit Design

Yes - the circuit exhibits exactly the same feedback method as can be found in the inverting opamp configuration.

26 replies | 707 view(s)

13th June 2018, 11:14

LvW replied to a thread Loop-gain calculation in Analog Circuit Design

So - you do not see any connection between output and input? I must admit, I see such a feedback path. Without it, the circuit would not work...

26 replies | 707 view(s)

13th June 2018, 10:00

LvW replied to a thread Loop-gain calculation in Analog Circuit Design

As mentioned by FvM: Lopp Gain=A*B. Do you know how to find the open-loop gain A?

26 replies | 707 view(s)

11th June 2018, 07:27

LvW replied to a thread Loop-gain calculation in Analog Circuit Design

So - the question remains: What is "B" in your circuit? What is the name of the quantity "B"?

26 replies | 707 view(s)

10th June 2018, 13:47

LvW replied to a thread Loop-gain calculation in Analog Circuit Design

Are you familiar with the loop gain definition? Do you know how you would measure/simulate the loop gain function?

26 replies | 707 view(s)

8th June 2018, 17:08

LvW replied to a thread What is the component that is represented by the letter F in the spice netlist? in Analog Circuit Design

"F" is a current-controlled current source (CCCS) - an artificial source of current.

2 replies | 174 view(s)

6th June 2018, 16:43

LvW replied to a thread Block diagram from circuit diagram in Elementary Electronic Questions

What is your question now?

15 replies | 543 view(s)

6th June 2018, 10:45

LvW replied to a thread Open loop gain and phase plotting in a closed loop system in Analog Integrated Circuit (IC) Design, Layout and Fabrication

I like to mention that none of your linked papers contain something we call "block diagram" - all are circuit diagrams. In general: In circuit...

5 replies | 323 view(s)

6th June 2018, 10:37

LvW replied to a thread Block diagram from circuit diagram in Elementary Electronic Questions

Klaus, thank you. I like to mention that none of the papers as linked in the above ref. contain something we call "block diagram" - all are...

15 replies | 543 view(s)

6th June 2018, 09:53

LvW replied to a thread Block diagram from circuit diagram in Elementary Electronic Questions

Here is a simple example how to convert a circuit diagram (more correct: all the equations describing the current-voltage relations) into a block...

15 replies | 543 view(s)

3rd June 2018, 11:41

Dominik Przyborowski replied to a thread Expression for gds as a function of VGS in weak inversion? in Analog Integrated Circuit (IC) Design, Layout and Fabrication

//edit - I see there is a problem with latex… My understanding of your idea is as follow: 1. the channel conductance is defined as: g_ds =...

5 replies | 263 view(s)

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