erikl
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Yesterday, 23:02shanmei started a thread bipolar active linear region in Analog Integrated Circuit (IC) Design, Layout and FabricationThe bipolar active linear (amplification) region is defined as Vbe>0 and Vbc<0, and the saturation region is defined as Vbe>0, and Vbc>0. Note that...2 replies | 88 view(s) -
Yesterday, 19:58Dominik Przyborowski replied to a thread Cascoding the two stage folded class AB ampliifer in Analog Integrated Circuit (IC) Design, Layout and FabricationAvailable headrom for you current sources is the vgs of output transistors and/or vgs of diodes on the rails. The minimum value of vds for 3 mosftes...1 replies | 78 view(s) -
25th March 2020, 12:31LvW replied to a thread the inductive impedance connected to drain can cause negative resistance at gate? in Analog Circuit DesignQuestion: Is the circuit which belongs to the quoted text an oscillator? Note that each oscillator with a feedback loop can also be seen as a...2 replies | 232 view(s) -
20th March 2020, 18:06Dominik Przyborowski replied to a thread Can't find "portAdaptor" in Virtuoso in Analog Integrated Circuit (IC) Design, Layout and FabricationLook for it in the spectre installation directory1 replies | 194 view(s)
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20th March 2020, 18:03Dominik Przyborowski replied to a thread wide band operational amplifer in Analog Integrated Circuit (IC) Design, Layout and FabricationIt's ordinary Miller OTA working in class A-AB. it is wideband because is not narrowband (it is not a joke). Don't pay too much attention to names....6 replies | 336 view(s)
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16th March 2020, 17:33Dominik Przyborowski replied to a thread Ideal switched capacitor circuit - voltage spikes in Analog Integrated Circuit (IC) Design, Layout and FabricationThe buety of numerical simulations... You can try VerilogA, apply some delay in vcvs, try to play with ahdlib blocks or simply use value() function...10 replies | 605 view(s)
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15th March 2020, 20:29Dominik Przyborowski replied to a thread Ideal switched capacitor circuit - voltage spikes in Analog Integrated Circuit (IC) Design, Layout and FabricationIf I understood properly, gain in vcvs is important. Try to use svcvs element instead of vcvs. Svcvs is vcvs with Laplace transfer function, so...10 replies | 605 view(s)
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15th March 2020, 17:34Dominik Przyborowski replied to a thread Ideal switched capacitor circuit - voltage spikes in Analog Integrated Circuit (IC) Design, Layout and FabricationI'm not sure whether is possible to remove discontinuity using relay element. If you need ideal system for behavioral modeling, why not write...10 replies | 605 view(s)
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15th March 2020, 17:28Dominik Przyborowski replied to a thread TSMC 0.18um Breakdown voltage in Analog Integrated Circuit (IC) Design, Layout and FabricationThere are various breakdown mechanism and we can distinguish: 1. Hard breakdown (permanent damage) 2. Soft breakdown Also, transistor is...8 replies | 466 view(s)
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14th March 2020, 22:21Dominik Przyborowski replied to a thread TSMC 0.18um Breakdown voltage in Analog Integrated Circuit (IC) Design, Layout and FabricationRead process documentation. There is an answer for your question. And be mercy ul for us. You even didn't mentioned what kind of transistors you...8 replies | 466 view(s)
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14th March 2020, 22:15Dominik Przyborowski replied to a thread Ideal switched capacitor circuit - voltage spikes in Analog Integrated Circuit (IC) Design, Layout and FabricationI am too lazy to calculate. What has bigger impact - gain of vcvs or rise time of clocks? If gain (gain of vcvs is 1M, cap divider is 1m product is...10 replies | 605 view(s)
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11th March 2020, 21:39erikl replied to a thread Self cascoded differential pair transistors in Analog Integrated Circuit (IC) Design, Layout and FabricationHi Junus, yes, I know his book and several papers by Johan Huijsing, very instructive ones, and I remember I've successfully used his class-AB...12 replies | 909 view(s)
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9th March 2020, 18:26erikl replied to a thread Self cascoded differential pair transistors in Analog Integrated Circuit (IC) Design, Layout and FabricationThanks a lot, Junus, for your summary. But you can be sure that I always read the whole thread before I answer. :smile: Re. self cascoding I've...12 replies | 909 view(s)
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8th March 2020, 18:53erikl replied to a thread Self cascoded differential pair transistors in Analog Integrated Circuit (IC) Design, Layout and FabricationMaybe it's a (somewhat obscure) abbreviation for self-biasing cascoded transistor. The upper transistor(s) need their own p-in-nwell substrates,...12 replies | 909 view(s)
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7th March 2020, 11:16Prashanthanilm replied to a thread Results for hierarchical LVS in ASIC Design Methodologies and Tools (Digital)In General, Suppose you give AND cell as hier cell. If the cell itself is failing, then it means the netlist and gds2 of Cell is not proper. If...1 replies | 289 view(s)
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3rd March 2020, 18:06Dominik Przyborowski replied to a thread DC operating output voltages of the Fully differential amplifier is not equal in Analog Integrated Circuit (IC) Design, Layout and FabricationI'm a bit uncertain whether bsim3 models contains any WPE or LOD parameters. It means, that if dc level differs between schematic and extracted...10 replies | 729 view(s)
About erikl
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- Analog Circuit Design
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- Biography:
- designed (and layouted) analog cells and IP's in various CMOS processes
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- Germany
- Interests:
- analog design in CMOS
- Occupation:
- on my own
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