erikl
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1st December 2019, 18:57Dominik Przyborowski replied to a thread [SOLVED] ADEXL simulation problem in cadence in Analog Integrated Circuit (IC) Design, Layout and FabricationThe simplest solution - use recommended system, in this case it is RHEL5 or 6. If in $HOME/.vnc-cds/eda:80.log is stated only such 4 lines, it...11 replies | 521 view(s) -
30th November 2019, 17:41Dominik Przyborowski replied to a thread [SOLVED] ADEXL simulation problem in cadence in Analog Integrated Circuit (IC) Design, Layout and FabricationI am considering myself as a lazy person, but ok. The issue is related to used by ADE XL mechanism of running job process by calling vnc protocol....11 replies | 521 view(s)
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30th November 2019, 14:58Dominik Przyborowski replied to a thread [SOLVED] ADEXL simulation problem in cadence in Analog Integrated Circuit (IC) Design, Layout and FabricationThe issue is well known and the solution you can find on this forum, too. Hint: look on the point 3 in message you're get (1921).11 replies | 521 view(s)
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30th November 2019, 10:26Dominik Przyborowski replied to a thread [SOLVED] ADEXL simulation problem in cadence in Analog Integrated Circuit (IC) Design, Layout and FabricationWhat is stated in job.log? What is your Linux distribution?11 replies | 521 view(s)
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29th November 2019, 21:37erikl replied to a thread Source follower design issue for cascoded two stage op-amp in Analog Integrated Circuit (IC) Design, Layout and FabricationWhy? The center voltage vo1 should be around VDD/2 (to achieve high swing), so you need that high shift 'cause VSG6 shouldn't get too much overdrive...5 replies | 383 view(s)
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29th November 2019, 20:46erikl replied to a thread Relating Transmitter dBm to uV/m and EIRP in RF, Microwave, Antennas and Optics14dBm ≙ 25mW, which generates 1.12V @ 50Ω - nearly your stated value.8 replies | 347 view(s)
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28th November 2019, 15:41erikl replied to a thread Rail to rail input folded operational amplifier in Analog Integrated Circuit (IC) Design, Layout and FabricationDepends. I used it for supply voltages of 1.0±0.2V and it worked well, as the Vth voltages of the process suited fine. With higher VDD this simple...3 replies | 333 view(s)
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28th November 2019, 15:02erikl replied to a thread Source follower design issue for cascoded two stage op-amp in Analog Integrated Circuit (IC) Design, Layout and FabricationOk, I see what you mean. Did I say that? I wrote weird terminology!5 replies | 383 view(s)
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27th November 2019, 22:46erikl replied to a thread Why BJT is used for voltage reference and not CMOS in Analog Circuit DesignActually such a current source produces a PTAT voltage reference, which - by comparison with a second PTAT voltage reference - can be converted into...4 replies | 246 view(s)
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27th November 2019, 21:47erikl replied to a thread Rail to rail input folded operational amplifier in Analog Integrated Circuit (IC) Design, Layout and FabricationBy W/L ratio (=1) between (P3,P4):(P1,P2) and (N3,N4):(N1,N2) resp. Don't forget: V2 & V3 must be supplied externally. Also, the common drain voltage...3 replies | 333 view(s)
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27th November 2019, 19:49erikl replied to a thread Source follower design issue for cascoded two stage op-amp in Analog Integrated Circuit (IC) Design, Layout and FabricationNo. The shift of the source follower MT1 of course is VSG (VSG1T in this weird terminology).5 replies | 383 view(s)
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27th November 2019, 19:11erikl replied to a thread Calibre LVS Extraction Report Warnings Question. in Analog Integrated Circuit (IC) Design, Layout and FabricationNo, I wouldn't think so. The warnings just inform that the power PATHCHK couldn't be performed because of unattached power labels and ports. So...1 replies | 199 view(s)
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27th November 2019, 18:49erikl replied to a thread In snapback mechanism how voltage reduces when parasitic NPN is turned ON? in Analog Integrated Circuit (IC) Design, Layout and FabricationOnce the n-p-n turns on means it is conducting and so presents a low resistance to the ESD event. Such an ESD event owns a certain energy E =...2 replies | 174 view(s)
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25th November 2019, 13:46MubarakKhan started a thread In snapback mechanism how voltage reduces when parasitic NPN is turned ON? in Analog Integrated Circuit (IC) Design, Layout and FabricationI'm reading the following paper about SNAPBACK ...2 replies | 174 view(s) -
14th November 2019, 13:47MubarakKhan started a thread What are biasing circuits? in Analog Integrated Circuit (IC) Design, Layout and FabricationWhat are biasing circuits? All circuits involving transistors are called biasing circuits (or) circuits used to generate reference signals like BGR...2 replies | 241 view(s)
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7th November 2019, 16:37Dominik Przyborowski replied to a thread Resistor mismatch hand calculation and simulation in Analog Integrated Circuit (IC) Design, Layout and FabricationThere is something called "error propagation law". This should be teacher at every school during laboratory measurement, so you should be able to...4 replies | 359 view(s)
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6th November 2019, 08:54ashrafsazid replied to a thread Resistor mismatch hand calculation and simulation in Analog Integrated Circuit (IC) Design, Layout and FabricationI expected a statistical answer. And sorry, I do not work with discrete elements.4 replies | 359 view(s)
About erikl
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- Area of specialization:
- Analog Circuit Design
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- Biography:
- designed (and layouted) analog cells and IP's in various CMOS processes
- Location:
- Germany
- Interests:
- analog design in CMOS
- Occupation:
- on my own
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