erikl
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Today, 03:32pragash started a thread Impact of parasitic capacitance and parastic inductance on DC and crystal oscillator in Electromagnetic Design and Simulationwe know that we need to avoid parasitic capacitance (electric field) and parasitic inductance (magnetic field) on the RF/Microwave circuit layout. My...1 replies | 40 view(s) -
19th August 2019, 21:25erikl replied to a thread Calibre Tool for DRC errors in Analog Integrated Circuit (IC) Design, Layout and FabricationThis depends on: - which physical design tool you are using - which DRC tool your PDK prefers - which (potential) foundry provides their Design...1 replies | 125 view(s)
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10th August 2019, 17:36xianweng started a thread Using VCVS as delay elements result in period signal rising and falling time changing in Analog Integrated Circuit (IC) Design, Layout and FabricationHi, everyone, My cadence version is IC6.1.7 and MMSIM version is 13.1. I am using VCVS as delay unit (I know there are some delay component in...2 replies | 316 view(s) -
3rd August 2019, 10:15LvW replied to a thread What does "great linearity" means for a ring oscillator? in Analog Circuit DesignOK - I see that there wasa misunderstanding between us. Of course, the sine function is - from the mathematically point of view - not a linear...8 replies | 359 view(s) -
2nd August 2019, 20:20LvW replied to a thread What does "great linearity" means for a ring oscillator? in Analog Circuit Design"A sine wave is non-linear" ??? Do you know the definition of linearity ? Sorry, but this is nonsense. The degree of non-linearity of an amplifier...8 replies | 359 view(s)
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2nd August 2019, 10:27LvW replied to a thread What does "great linearity" means for a ring oscillator? in Analog Circuit DesignI rather think that te term "linearity" concerns the QUALITY of the oscillation signal (ideal: Sinusoidal). Each amplifier with a "good linearity"...8 replies | 359 view(s)
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1st August 2019, 07:52pragash started a thread TRL calibration kit for PNA series (E8358A) in Robotics and Automation Forumi have fabricated TRL calibration kits for my design. however, i figured that it's not straight forward to do TRL calibration in the PNA E8358A. we...0 replies | 170 view(s)
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30th July 2019, 19:47Hi What you have done , is a way that everybody will use to see ripple voltage and noise , separately . Technically consider that mode ,...3 replies | 684 view(s) -
29th July 2019, 20:02shanmei replied to a thread input current of the integrator in Analog Integrated Circuit (IC) Design, Layout and FabricationSure, the feedback loop of force negative and positive node of the opamp to be equal. Input current charges the negative node of the opamp,...15 replies | 807 view(s)
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29th July 2019, 18:03shanmei replied to a thread input current of the integrator in Analog Integrated Circuit (IC) Design, Layout and FabricationThank you for all your feedback. Why node Vx ( negative input node of the integator) does not change when the current charges Vx node, because...15 replies | 807 view(s)
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28th July 2019, 23:34Hi As i know , you can go through LT (Linear technology productions ) chips . I used many led drivers and current controller chips from that...4 replies | 555 view(s)
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27th July 2019, 02:00shanmei replied to a thread input current of the integrator in Analog Integrated Circuit (IC) Design, Layout and FabricationSorry I still do not understand. Assume the input current is dc current, it can not go through the feedback capacitor as I1, and it can not go...15 replies | 807 view(s)
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27th July 2019, 00:55pragash replied to a thread [CST] How to simulate Radiated Spurious Emissions (RSE) in Electromagnetic Design and Simulationi would like to predict radiated spurious emission test failure via EMC/EMI simulation.2 replies | 249 view(s)
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26th July 2019, 18:04shanmei replied to a thread input current of the integrator in Analog Integrated Circuit (IC) Design, Layout and FabricationThank you for the feedback. Sure, a reset switch is needed to prevent saturation. But during the integration process, how can the current "goes...15 replies | 807 view(s)
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26th July 2019, 16:10erikl replied to a thread Nand gate using bsim-cmg in Analog Integrated Circuit (IC) Design, Layout and FabricationEither hspice didn't find the .include "modelcard.xmos" modelcards, or these modelcards do not contain the therein used nmos1 respectively pmos1...1 replies | 261 view(s)
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26th July 2019, 14:30shanmei started a thread input current of the integrator in Analog Integrated Circuit (IC) Design, Layout and FabricationAn integrator is built with an opamp and a feedback capacitor acossing the output node and negative input node of the opamp. The input current...15 replies | 807 view(s)
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26th July 2019, 10:35pragash started a thread [CST] How to simulate Radiated Spurious Emissions (RSE) in Electromagnetic Design and Simulationi know there is a way to simulate radiated spurious emissions using CST. can anyone have methodology documents or know how to do it step by step?2 replies | 249 view(s)
About erikl
Basic Information
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- Area of specialization:
- Analog Circuit Design
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- Biography:
- designed (and layouted) analog cells and IP's in various CMOS processes
- Location:
- Germany
- Interests:
- analog design in CMOS
- Occupation:
- on my own
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