erikl
Super Moderator
Find latest posts
View Articles
View Blog EntriesMini Statistics
- Join Date
- 9th September 2008
- Last Activity
- 16th May 2020 20:36
- Blog Entries
- 0
- Avatar
More 123 Friends
Awards
No Awards.
Achievements
7 years registeredRecent Visitors
- deepsetan,
- Easy peasy,
- KlausST,
- Luis_rr,
- mitroialin,
- MubarakKhan,
- rajender1501,
- rfx,
- tareq1232001,
- VcitorC
- Tab Content
- erikl's Activity
- About Me
- Friends
- Experience
-
Older Activity
-
22nd May 2020, 16:18LvW replied to a thread Will a filter block this waveform? in Hobby Circuits and Small Projects ProblemsA filter cannot "block" any waveform. And a filter also cannot "block" frequencies. It only can attenuate some unwanted frequencies - and as a...25 replies | 697 view(s) -
18th May 2020, 20:24Dominik Przyborowski replied to a thread CADENCE is disabling functions alone in ASIC Design Methodologies and Tools (Digital)Do you know what is the purpose of this toolbar? What do you mean it doesn't work?6 replies | 383 view(s) -
18th May 2020, 20:21Dominik Przyborowski replied to a thread CADENCE: layout error in ASIC Design Methodologies and Tools (Digital)So your statement from post #3 was not true. If you look on properties of both libraries NAND and INVERTER (by RMB→properties in Lib Manager), you...8 replies | 443 view(s)
-
18th May 2020, 19:16Dominik Przyborowski replied to a thread CADENCE: layout error in ASIC Design Methodologies and Tools (Digital)So do it again, but this time do it properly. You have clear message, that cdsTechDefLib is currently attached to library NAND. Reattach library to...8 replies | 443 view(s)
-
18th May 2020, 15:31Dominik Przyborowski replied to a thread CADENCE: layout error in ASIC Design Methodologies and Tools (Digital)Attach or reference your design library to correct technology library.8 replies | 443 view(s)
-
16th May 2020, 16:23The dynamic (differential) output resistance ro of a transistor is the inverse slope of the (relatively flat) output curves ID=f(VDS). Hence, this...3 replies | 434 view(s)
-
16th May 2020, 09:07LvW replied to a thread Simulating AC performance of the amplifier with switched capacitor circuit in Analog Integrated Circuit (IC) Design, Layout and FabricationJunus...I have sentyou an email message11 replies | 811 view(s)
-
15th May 2020, 17:34LvW replied to a thread Simulating AC performance of the amplifier with switched capacitor circuit in Analog Integrated Circuit (IC) Design, Layout and FabricationBut it is important to know that methods I was refering to preserve the characteristics of sampled data system (periodic response of the clock period...11 replies | 811 view(s)
-
15th May 2020, 16:58Dominik Przyborowski replied to a thread Layout of big transistors in Analog Integrated Circuit (IC) Design, Layout and FabricationIt is process dependent. Gate leakage with poly resistance makes upper limit for width. LWR, LER and LOD strain makes lower limit for finger...3 replies | 317 view(s)
-
15th May 2020, 16:40Dominik Przyborowski replied to a thread Simulating AC performance of the amplifier with switched capacitor circuit in Analog Integrated Circuit (IC) Design, Layout and FabricationLinearization is one method as LvW mentioned. However, if you have SpectreRF license you might try to use periodic simulations (pss, pac, pstb or...11 replies | 811 view(s)
-
15th May 2020, 08:16LvW replied to a thread Simulating AC performance of the amplifier with switched capacitor circuit in Analog Integrated Circuit (IC) Design, Layout and FabricationNelin B.D.: "Analysis of Switched-Capacitor Networks using general purpose circuit simulation programs.", IEEE Trans. Circuit and Systems, vol...11 replies | 811 view(s)
-
14th May 2020, 07:33LvW replied to a thread Simulating AC performance of the amplifier with switched capacitor circuit in Analog Integrated Circuit (IC) Design, Layout and FabricationSwitched-capacitor circuits are sampled data systems. They are a kind of "bridge" between analog and digital systems (time discrete but amplitude...11 replies | 811 view(s)
-
6th May 2020, 20:50Dominik Przyborowski replied to a thread Cascoding the two stage folded class AB ampliifer in Analog Integrated Circuit (IC) Design, Layout and FabricationAssumptions: 1. All guys has the same dimensions (absolute, not ratio) 2. ×3 stacked guys below diode are triodes with total V_DS equal to VDS_SAT...21 replies | 3379 view(s)
-
6th May 2020, 19:15Dominik Przyborowski replied to a thread Simulating Gain/PM of Constant GM Current Reference in Cadence in Analog Integrated Circuit (IC) Design, Layout and FabricationYes, there is a lot of way to do it. Closed loop system is a principle of control system theory and has a long history of research and education....12 replies | 898 view(s)
-
4th May 2020, 18:25There are so called "state-variable" 2nd-oder Filter topologies (e.g. KHN or Tow-Thomas) which are able to provide - at the same time - three...34 replies | 2787 view(s)
-
3rd May 2020, 14:58Dominik Przyborowski replied to a thread Difference between Sample/Value Function in Cadence Spectre in Analog Integrated Circuit (IC) Design, Layout and FabricationDear Puppet123 Our dear friend Pancho sometimes makes impression to be harsh, but reading posts of some users, I can admire Pancho patience and...10 replies | 1407 view(s)
About erikl
Basic Information
Areas of Interest
- Area of specialization:
- Analog Circuit Design
Optional Info
- Biography:
- designed (and layouted) analog cells and IP's in various CMOS processes
- Location:
- Germany
- Interests:
- analog design in CMOS
- Occupation:
- on my own
Statistics
Total Posts
- Total Posts
- 8,112
- Posts Per Day
- 1.90
General Information
- Last Activity
- 16th May 2020 20:36
- Join Date
- 9th September 2008
Helpful Postings
- Has Rated
- 168
- Post Rated
- Rated helpful 2676 out of 2676 times
123 Friends
Showing Friends 1 to 10 of 123
Experience
Points
- Points
- 52,148
- Level
- 55
Level up completed
- Level up completed
- 79%
- Points required
- 402
Activity
- Activity
- 0%
- Activity last 30 days
- 0%
- Activity last 7 days
- 4.0%
Points
All Points for user
- Points for User
- 15,580
- Points for Reputation
- 12,846
- Points for every day since registration
- 2,407
- Points for Friends
- 327
All Points for threads
- Points for threads
- 462
- Points for Threads
- 8
- Points for Social Group Discussions
- 6
- Points for tagging threads
- 432
- Points for replies
- 16
All Points for posts
- Points for Posts
- 36,106
- Points for Posts
- 22,695
- Points for Social Group Messages
- 6
- Average Posts per Day
- 1.00
- Helpful Answers
- 13,405
All Points for miscellaneous
- Points for Misc
- 0
Activities
2nd May 2020
- 03:06 erikl has earned 5 Points for Posts points
- 03:06 erikl has earned 3 Points for threads points
- 03:06 erikl has earned 28 Points for User points
12th March 2020
- 03:05 erikl has earned 3 Points for Posts points
- 03:05 erikl has earned 1 Points for User points
10th March 2020
- 03:06 erikl has earned 8 Points for Posts points
- 03:06 erikl has earned 2 Points for User points
9th March 2020
- 03:06 erikl has earned 24 Points for User points
- 03:06 erikl has earned 18 Points for Posts points
2nd February 2020
- 03:06 erikl has earned 1 Points for threads points
- 03:06 erikl has earned 1 Points for User points
1st February 2020
- 03:06 erikl has earned 3 Points for Posts points
31st January 2020
- 03:06 erikl has earned 5 Points for User points
- 03:06 erikl has earned 13 Points for Posts points
30th January 2020
- 03:06 erikl has earned 3 Points for Posts points
29th January 2020
- 03:06 erikl has earned 8 Points for Posts points
- 03:06 erikl has earned 7 Points for User points
- 03:06 erikl has earned 1 Points for threads points
20th January 2020
- 03:05 erikl has earned 31 Points for User points
- 03:05 erikl has earned 18 Points for Posts points
Show Activities from all Users