FvM
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Yesterday, 23:24FvM replied to a thread VFD to control 3 phase AC induction motor 400V 6000 rpm in Power ElectronicsI'm already stumbling upon the motor specification. What is it? 6000 rpm at 100 Hz? Industry standard motors are specified for either 50 or 60 Hz.6 replies | 184 view(s) -
Yesterday, 22:03FvM replied to a thread 3 phase 400Vac 5000W Full bridge converter power factor correction Buck or Boost type in Power ElectronicsI don't know what's sufficient for x1.3 peak current, depends on the DC/DC stiffness. You should simulate the behaviour accurately before fixing the...37 replies | 1057 view(s)
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Yesterday, 19:29FvM replied to a thread 3 phase 400Vac 5000W Full bridge converter power factor correction Buck or Boost type in Power ElectronicsNo. Without energy storage, each single phase converter has output current swinging between 0 and 2*Iavg. You can either implement energy storage...37 replies | 1057 view(s)
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Yesterday, 15:48I would say it depends how timing critical is the setting of read_en <= 1'b1 in your design and how frequently condition1 is toggling. It is always...1 replies | 85 view(s) -
Yesterday, 11:44dpaul replied to a thread Verilog code to find modular inverse value in PLD, SPLD, GAL, CPLD, FPGA DesignA quick online search comes up with some links. I found this one sleek & short - https://github.com/NetFPGA/netfpga/wiki/VerilogCodingGuidelines ...5 replies | 136 view(s)
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Yesterday, 09:47Sure. Any operation point with asymmetric duty cycle. Peak current translates with winding ratio, average and rms does not.9 replies | 163 view(s)
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Yesterday, 09:43dpaul replied to a thread Verilog code to find modular inverse value in PLD, SPLD, GAL, CPLD, FPGA DesignNo you have not. Please read a good tutorial on Verilog as to how should one write synth code. I stop looking further at your code when I see that...5 replies | 136 view(s)
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Yesterday, 09:38FvM replied to a thread 3 phase 400Vac 5000W Full bridge converter power factor correction Buck or Boost type in Power ElectronicsThe threefold single phase solution has been already discussed at the begin of this thread. It's feasible but has some disadvantages. E.g. the energy...37 replies | 1057 view(s)
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Yesterday, 09:21No, both average and rms are modified by the primary to secondary duty cycle ratio.9 replies | 163 view(s)
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Yesterday, 08:42That's true for a transformer with negligible magnetizing current but not for a flyback, where the output current is sourced by transformer...9 replies | 163 view(s)
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20th March 2019, 15:37It's not actually clear if the original post is talking about limited accuracy of the NTC sensor or errors of the ADC and measurement circuit. You...5 replies | 107 view(s)
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20th March 2019, 14:58FvM replied to a thread CMRR simulation for fully differential amplifier in Analog Integrated Circuit (IC) Design, Layout and FabricationThe basic idea of the "simple" CMRR setups is to use the same configuration as in actual amplifier application. If it's a 4 resistor configuration,...20 replies | 345 view(s)
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20th March 2019, 14:44dpaul replied to a thread [moved] Need help writing equations in Verilog A. My first code in Verilog A. in Analog Integrated Circuit (IC) Design, Layout and FabricationHi, this is the Digital Design and Embedded Programming forum. You won't get any help here on VerilogA! A Mod should be shifting this to the...3 replies | 174 view(s)
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19th March 2019, 23:19Regular CMOS logic won't be able to run from 0.38 V. Special circuit, preferably with depletion mode transistors is required for the cold start...2 replies | 144 view(s)
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19th March 2019, 19:03FvM replied to a thread CMRR simulation for fully differential amplifier in Analog Integrated Circuit (IC) Design, Layout and FabricationSetup 1 is suggested in manufacturer datasheets, e.g. from Analog.20 replies | 345 view(s)
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19th March 2019, 16:49FvM replied to a thread Voltage degradation in Hold mode of the bootstrap switch ? in Analog Integrated Circuit (IC) Design, Layout and FabricationThe effect is called "hold step", happens due to switch charge injection, in other words Cgd respectively Cgs of the switch MOSFET.2 replies | 84 view(s)
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19th March 2019, 16:41FvM replied to a thread CMRR simulation for fully differential amplifier in Analog Integrated Circuit (IC) Design, Layout and FabricationIn practice, you don't need to measure differential mode gain to determine CMRR because it's defined by the feedback network with sufficient accuracy.20 replies | 345 view(s)
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19th March 2019, 16:37I would expect antiparallel diodes instead of two diodes with same polarity. What's your specification for the limiter (output versus input level,...3 replies | 110 view(s)
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19th March 2019, 12:08Industry standard level control relays for electrodes have adjustable threshold range, e.g. 1k - 100k resistance. It's suitable for drinking water,...11 replies | 492 view(s)
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19th March 2019, 10:17Basys 3 has adequate num of Pmod connectors on board. So why not choose a Pmod based colour sensor for easy integration?...3 replies | 151 view(s)
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19th March 2019, 09:02FvM replied to a thread CMRR simulation for fully differential amplifier in Analog Integrated Circuit (IC) Design, Layout and FabricationThink simple. To measure CMRR, you'll apply a common mode signal and measure the respective transfer function.20 replies | 345 view(s)
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18th March 2019, 23:30There's much literature about oil and gas filled HV switches, some results can be probably applied to sparc gap behaviour. I agree with wwfeldman...11 replies | 394 view(s)
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18th March 2019, 23:20FvM replied to a thread How to make a 5V negative supply using the LM2576 regulator in Analog Circuit DesignThe shown 200 mV noise is just what you can expect from the simple circuit and layout. The 80 MHz ringing is mostly caused by the switching schottky...4 replies | 179 view(s)
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18th March 2019, 23:00I suggest to study high voltage ultrasonic echo sounder circuits to get an idea how to implement voltage clamping in the receiver path. They often...7 replies | 301 view(s)
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18th March 2019, 22:11That's o.k. Problem is unsuitable combination of kp and ki, as already stated. kp=1 seems generally problematic. A controller with practical use has...5 replies | 221 view(s)
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18th March 2019, 14:05In case of doubt, derive the parameters in transient analysis.6 replies | 189 view(s)
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18th March 2019, 12:56FvM replied to a thread How to design an class d output filter ( active filter )? in Analog Circuit DesignPurpose of the design is still mysterious. You may use a SD-modulator to drive a three-level class D amplifier and place a passive LC filter towards...7 replies | 218 view(s)
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18th March 2019, 12:45Please specify "control speed". - on/off control - switching between discrete speeds - continuous speed variation In addition, what's expected...4 replies | 264 view(s)
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