FvM -

Yesterday, 22:09

FvM replied to a thread MBUS (Meter Bus) Master Analog Circuit in Analog Circuit Design

EN 1434-3 has MBUS master reference schematics.

3 replies | 70 view(s)

Yesterday, 18:57

FvM replied to a thread High voltage, big capacitor charger: Flyback vs Push-Pull in Power Electronics

Flyback is the standard solution e.g. for xenon flashlight power supply since half a century. It doesn't need any complicated control circuit except...

2 replies | 75 view(s)

Yesterday, 18:44

FvM replied to a thread D Flipflop with enable does not have the else part in RTL in the if-else statement in ASIC Design Methodologies and Tools (Digital)

I think, the conclusion is incorrect or at least misleading in so far that a flipflop won't be generated only in this case, but in any case with or...

8 replies | 602 view(s)

Yesterday, 08:50

FvM replied to a thread Transistor recommendation sought in Hobby Circuits and Small Projects Problems

A 800 mA high side switch doesn't necessarily need heat sinking, only if you select a switch with too high voltage drop. It's amazing that you still...

16 replies | 299 view(s)

Yesterday, 08:33

FvM replied to a thread SWR meter how its works? in Analog Circuit Design

Using AD8302, you don't need a bridge circuit, just connect voltage and current channel to the detector.

5 replies | 199 view(s)

26th May 2018, 23:11

FvM replied to a thread Flyball spin up time in Mathematics and Physics

With moveable arms, the moment of inertia is variable. Lets the flyball spin up faster in the beginning but it slows down when the arms move...

3 replies | 135 view(s)

26th May 2018, 18:03

FvM replied to a thread D Flipflop with enable does not have the else part in RTL in the if-else statement in ASIC Design Methodologies and Tools (Digital)

It's more simple. The below code already implements a DFF always @(posedge clk ) Q<=d;

8 replies | 602 view(s)

26th May 2018, 17:52

FvM replied to a thread Divison by 2 syntesizable RTL coding in ASIC Design Methodologies and Tools (Digital)

Rightshifting in0 bit input gives zero result.

4 replies | 86 view(s)

26th May 2018, 14:28

FvM replied to a thread [Moved] LTspice not working in Windows 10 in Software Problems, Hints and Reviews

There are several discussions at the unofficial LTspice support forum https://groups.yahoo.com/neo/groups/LTspice/info It's assumed so far that...

9 replies | 244 view(s)

26th May 2018, 10:42

FvM replied to a thread Electrical noise generated by sealed lead-acid batteries in Power Electronics

May be it's the battery. But before blaming it, I would expect significant measurements verifying that it's not just the load current ripple or some...

3 replies | 112 view(s)

26th May 2018, 09:51

FvM replied to a thread Read operation of a memory and clock cycles in ASIC Design Methodologies and Tools (Digital)

A synchronous RAM without output registers provides the read data shortly after latching the read address.

2 replies | 64 view(s)

26th May 2018, 09:25

FvM replied to a thread D Flipflop with enable does not have the else part in RTL in the if-else statement in ASIC Design Methodologies and Tools (Digital)

Your first question has already been answered in both replies. If intended as DFF description, it's erroneous. According to Verilog rules,...

8 replies | 602 view(s)

25th May 2018, 16:12

FvM replied to a thread CCM BOOST PFC ltspice simulation confusing point in Power Electronics

The PFC control algorithm needs some explanation, where did you get it?

2 replies | 82 view(s)

25th May 2018, 15:55

FvM replied to a thread D Flipflop with enable does not have the else part in RTL in the if-else statement in ASIC Design Methodologies and Tools (Digital)

Latches are generated in combinational (level sensitive event triggered) always block. It's just fine this way.

8 replies | 602 view(s)

25th May 2018, 13:42

dpaul replied to a thread [moved] Simulator and synthesis tool required in PLD, SPLD, GAL, CPLD, FPGA Design

They accept any mail ID. If you are not working, then just put some data there like, "abcd" in the Company field. OP, you can download Xilinx...

6 replies | 214 view(s)

25th May 2018, 11:42

FvM replied to a thread Thermal noise reduction technique in Analog Circuit Design

For an amplifier, you want to calculate input referred noise.

5 replies | 129 view(s)

25th May 2018, 11:39

FvM replied to a thread STPM10 Data active energy calculation problem in Analog Circuit Design

Signals are named SCL and SDA, but it's a SPI interface. Timing of read transaction looks correct at first sight, but I don't know how you are...

6 replies | 98 view(s)

25th May 2018, 11:27

FvM replied to a thread Flyback converter EMI vs capacitive touch buttons in Power Electronics

Did you try state-of-the-art "Y" capacitors between secondary and primary ground or mains L and N wire? Most off-the-shelf DC/DC converters have it.

11 replies | 152 view(s)

24th May 2018, 19:21

FvM replied to a thread What is output voltage of 3 phase vfd in Power Electronics

The second and third waveform look very different from any expectable inverter output. No idea how you managed top get it.

25 replies | 553 view(s)

24th May 2018, 19:19

FvM replied to a thread Crystal oscilator and load capacitor? in Analog Circuit Design

Did you use TTL gates? They have asymmetric output and behave completely different than 74HC gates. That's the reason for asymmetrical output, not...

14 replies | 253 view(s)

24th May 2018, 19:15

FvM replied to a thread D flip flop RTL without Qbar in ASIC Design Methodologies and Tools (Digital)

At the gate level, a DFF is made of cascaded inverting gates and transfer gates. So either if you expose it or not, there will be an internal qbar...

7 replies | 104 view(s)

24th May 2018, 11:04

FvM replied to a thread Wish to see if electronics products are immune to noise in Power Electronics

No. Devices required to comply with EMC standards will be tested with respective IEC 61000-4-x methods. Particularly 4-4 (Burst) and 4-6 (Conducted...

4 replies | 133 view(s)

24th May 2018, 10:49

FvM replied to a thread Clock gating and cdc on clock_req in ASIC Design Methodologies and Tools (Digital)

You surely can do exactly this. If not, there's probably a lack of specification. What is the expected behavior of the individual signals OR-ed...

3 replies | 175 view(s)

24th May 2018, 10:32

FvM replied to a thread Crystal oscilator and load capacitor? in Analog Circuit Design

The circuit dimensioning has to be related to the effective load capacitance specified in the crystal datasheet. The actual circuit capacitance is...

14 replies | 253 view(s)

24th May 2018, 10:13

FvM replied to a thread frequency shift between simulation and measurements in RF, Microwave, Antennas and Optics

Capacitors are apparently 0603 size which is huge for 9 GHz range. If the used model includes the series inductance, it's unlikely to be valid for...

17 replies | 299 view(s)

24th May 2018, 08:57

FvM replied to a thread STPM10 Data active energy calculation problem in Analog Circuit Design

SPM10 active energy register holds only 20 bit data, 2039592 is an 21 bit value (0x1F1F28), so something's wrong with your software.

6 replies | 98 view(s)

24th May 2018, 08:03

FvM replied to a thread Crystal oscilator and load capacitor? in Analog Circuit Design

I have no doubts that the circuit is somehow oscillating. Using buffered 74HC04 makes the exact circuit behavior unpredictable, I'm not particularly...

14 replies | 253 view(s)

24th May 2018, 07:52

FvM replied to a thread Sonicator not working in Service Manuals, Requests, Repair Tips

Not the intended operation mode. There must be 35 kHz signal. Defective power stage?

3 replies | 227 view(s)

23rd May 2018, 17:05

FvM replied to a thread Crystal oscilator and load capacitor? in Analog Circuit Design

No idea, hardly based on manufacturer suggestions, see this Epson application circuit: Notice that the oscillator circuit should use 74HC04U...

14 replies | 253 view(s)