FvM
Super Moderator
Find latest posts
View Articles
View Blog EntriesMini Statistics
- Join Date
- 22nd January 2008
- Last Activity
- Yesterday 22:19
- Blog Entries
- 0
More 128 Friends
1 Groups
Join Groups 0 Permission Groups
FvM is not a member of any public groups
Awards
1st Helpful MemberAchievements
7 years registered- Tab Content
- FvM's Activity
- About Me
- Friends
- Experience
-
Older Activity
-
Yesterday, 15:44Good idea. I guess you have input or output AC coupling and the bias point is shifting when the input signal is rectified in saturated operation.3 replies | 98 view(s) -
Yesterday, 08:54FvM replied to a thread How good is ultiboard? in PCB Routing Schematic Layout software and SimulationFirstly I'd like to hint to a sticky thread on top of this forum...3 replies | 104 view(s)
-
Yesterday, 08:02FvM replied to a thread Power harvester evaluation board and antenna issues in Elementary Electronic QuestionsAre you serious? Using an amplifier with energy harvesting? Did you understand the basic idea? - - - Updated - - - Energy harvesting is...2 replies | 79 view(s)
-
18th September 2019, 16:42There may be good reasons to implement a linear (class AB) amplifier for your purposes, I don't apply to decide yes or no. You have implicitly...7 replies | 293 view(s)
-
18th September 2019, 12:21FvM replied to a thread In distributed amplifiers, is it total input capacitance of the gain stage or Cgs in RF, Microwave, Antennas and OpticsSeriously, does the discussion about terms help in any way to answer the original question? Does the term "artificial transmission line" clarify...4 replies | 277 view(s)
-
18th September 2019, 11:49The swing example is inappropriate for the original gyroscope problem. Swing involves periodical transfer between potential and kinetic energy. Work...42 replies | 1021 view(s)
-
18th September 2019, 10:50dpaul replied to a thread How do i read or write to ram address given in datasheet? using verilog in PLD, SPLD, GAL, CPLD, FPGA DesignAs mentioned above, you need to provide the bus info connecting the RAM. Then you need to drive those bus signals for READ or WRITE cases.2 replies | 134 view(s) -
18th September 2019, 08:19Doesn't sound bad in general, but some details aren't quite clear. Do you mind to share a CAD drawing of the intended sensor mount?1 replies | 153 view(s)
-
17th September 2019, 22:02FvM replied to a thread Operational amplifier driving capability test in Analog Integrated Circuit (IC) Design, Layout and FabricationThe described setup (setting a fixed output voltage) doesn't fully test "driving capability", you want to evaluate the available output current over...11 replies | 221 view(s)
-
17th September 2019, 18:33FvM replied to a thread Problem adding reset to master slave D-FF for phase detector in ASIC Design Methodologies and Tools (Digital)In a regular master slave FF, the asynchronous reset signal is expected to immediately reset both stages independent of the clock state, that's what...5 replies | 311 view(s)
-
17th September 2019, 16:03Individual harmonics have different limit values. THD isn't enough. As for the general question, FFT is supported by most modern digital scopes....11 replies | 781 view(s)
-
17th September 2019, 09:54FvM replied to a thread Higher Current Consumption than expected with AFE and embedded Flash in IoT - Internet of ThingsHard to give less information… Where do you see the current peak and when? You should be able to trace the current path down to the component...5 replies | 122 view(s)
-
17th September 2019, 09:31FvM replied to a thread [SOLVED] Suppressing the spacing in $fwrite command of Verilog in PLD, SPLD, GAL, CPLD, FPGA DesignReview System Verilog language reference, paragraph 21.2.1.3 Size of displayed data. It's regular C format specifier syntax, by the way.3 replies | 136 view(s)
-
16th September 2019, 16:24It depends. Some thermal pastes with high thermal conductivity are metal filled and also electrically conductive. But as far as I can see from the...26 replies | 766 view(s)
-
16th September 2019, 13:58FvM replied to a thread [SOLVED] AMS simulation of D-FF in Analog Integrated Circuit (IC) Design, Layout and FabricationThere's no clock signal fed to your circuit, respectively output is uninitialized.. Confusingly you are providing a multi level ("electrical")...2 replies | 157 view(s)
-
16th September 2019, 12:59The order of magnitude sounds reasonable. Obviously the numbers have been empirically validated, but your antenna geometry may be different. You...8 replies | 410 view(s)
-
16th September 2019, 10:25Adjustment is either at the probe or the probe connector. Why don't you read the manual?26 replies | 766 view(s)
-
15th September 2019, 15:10FvM replied to a thread Is there possibility to force a filter topology in DA_LClowpassMatch in ADS? in RF, Microwave, Antennas and Opticsfrdm90 didn't yet release a matching bandwidth specification. I presume, it's not possible to achieve a higher bandwidth with LC network for the...24 replies | 716 view(s)
-
15th September 2019, 13:53Besides unsuitable probe connection it may be dropping DC supply. I won't care about it much. Overshoot is much more a problem. It probably kills the...26 replies | 766 view(s)
-
15th September 2019, 12:53How can you measure with different ground connection for blue and yellow trace simultaneously? The real circuit must be somehow different. - - -...26 replies | 766 view(s)
-
15th September 2019, 11:56No. I referred to the isolation capacitance, e.g. the transformer interwinding capacitance. The linear voltage regulator circuit is O.K. But it's not...26 replies | 766 view(s)
-
15th September 2019, 09:55O.K., you can tune a diff mode filter to reject a particular frequency, at cost of wideband suppression. If it helped in a special case, it's surely...14 replies | 2132 view(s)
-
15th September 2019, 09:48There's no DC bus in a "direct converter", which constitutes already some of the circuit problems. It's not clear where you measure the "IGBT...26 replies | 766 view(s)
-
14th September 2019, 16:23Part of your points have been already discussed in the previous thread. Surely not. A choke has maximal impedance at it's SRF, respectively...14 replies | 2132 view(s)
-
14th September 2019, 11:46FvM replied to a thread Problem adding reset to master slave D-FF for phase detector in ASIC Design Methodologies and Tools (Digital)I don't understand what you consider "wrong" in the posted simulation waveforms. I don't recognize missing pulses or similar artefacts. Please...5 replies | 311 view(s)
-
14th September 2019, 09:49Sure, but the problem is at least of theoretical interest. Kajunbee's empirical observation that braking the precession slows down the gyro rotation...42 replies | 1021 view(s)
About FvM
Basic Information
Optional Info
- Location:
- Bochum, Germany
- Interests:
- Analog, DSP, Power electronics and more
Statistics
Total Posts
- Total Posts
- 45,270
- Posts Per Day
- 10.63
General Information
- Last Activity
- Yesterday 22:19
- Join Date
- 22nd January 2008
Helpful Postings
- Has Rated
- 2095
- Post Rated
- Rated helpful 13422 out of 13422 times
128 Friends
Showing Friends 1 to 10 of 128
Experience
Points
- Points
- 259,307
- Level
- 100
Level up completed
- Level up completed
- 0%
- Points required
- 0
Activity
- Activity
- 100.0%
- Activity last 30 days
- 100.0%
- Activity last 7 days
- 100.0%
Points
All Points for user
- Points for User
- 58,211
- Points for Reputation
- 53,644
- Points for every day since registration
- 4,174
- Points for Friends
- 387
- Points for posting Visitormessages
- 2
- Points for filling profile
- 4
All Points for threads
- Points for threads
- 3,850
- Points for Threads
- 113
- Points for tagging threads
- 3,612
- Points for replies
- 125
All Points for posts
- Points for Posts
- 197,246
- Points for Posts
- 130,002
- Points for uploading Attachments
- 54
- Average Posts per Day
- 10.00
- Helpful Answers
- 67,190
All Points for miscellaneous
- Points for Misc
- 0
Activities
20th September 2019
- 03:06 FvM has earned 3 Points for threads points
- 03:06 FvM has earned 3 Points for User points
- 03:06 FvM has earned 14 Points for Posts points
19th September 2019
- 03:06 FvM has earned 4 Points for User points
- 03:06 FvM has earned 22 Points for Posts points
18th September 2019
- 03:05 FvM has earned 5 Points for User points
- 03:05 FvM has earned 25 Points for Posts points
- 03:05 FvM has earned 1 Points for threads points
17th September 2019
- 03:05 FvM has earned 2 Points for User points
- 03:05 FvM has earned 17 Points for Posts points
- 03:05 FvM has earned 1 Points for threads points
16th September 2019
- 03:05 FvM has earned 3 Points for User points
- 03:05 FvM has earned 23 Points for Posts points
- 03:05 FvM has earned 1 Points for threads points
15th September 2019
- 03:05 FvM has earned 4 Points for User points
- 03:05 FvM has earned 2 Points for threads points
- 03:05 FvM has earned 19 Points for Posts points
14th September 2019
- 03:05 FvM has earned 5 Points for User points
- 03:05 FvM has earned 13 Points for Posts points
13th September 2019
- 03:06 FvM has earned 6 Points for User points
Show Activities from all Users