FvM
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Yesterday, 19:59For the said measurement application (high side gate voltage), you need really high CMRR and a probe design that doesn't send common mode currents...2 replies | 82 view(s) -
Yesterday, 14:07dpaul replied to a thread Interface Logic Model in Synosys is obsolete in ASIC Design Methodologies and Tools (Digital)What does the command reference manual say? Have you looked there?1 replies | 168 view(s) -
Yesterday, 14:02dpaul replied to a thread Get some advice and tips to design ETHERNET switch or even TSN switch on FPGA in PLD, SPLD, GAL, CPLD, FPGA DesignI know that and assumed the OP knows the difference. If he is a beginner in this area, it makes more sense for him to 1st understand how Ethernet...5 replies | 197 view(s)
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Yesterday, 11:04I agree about using RS-422 or RS-485. It can work over many km in a party line topology with correct end termination. I'm however surprised that...10 replies | 301 view(s)
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Yesterday, 10:36What's the opto triac type? I suggest an RCR filter/snubber circuit like below to prevent parasitic triggering. R2 can be reduced to 50 to 200 ohm...5 replies | 158 view(s)
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23rd January 2020, 23:59Suggest you get self-triggering of opto triac or main triac by high dv/dt. That's likely to happen with inductive load, RC filters for the opto...5 replies | 158 view(s)
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23rd January 2020, 17:17FvM replied to a thread Configuring ICE40 FPGA directly from ESP32 uC rather than using dedicated flash IC in PLD, SPLD, GAL, CPLD, FPGA Design"Slave SPI mode" in the configuration manual refers to operating the uC as SPI master and ICE40 as slave which is most likely the easier way.7 replies | 222 view(s)
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23rd January 2020, 16:07dpaul replied to a thread Get some advice and tips to design ETHERNET switch or even TSN switch on FPGA in PLD, SPLD, GAL, CPLD, FPGA DesignYou need the understand the concepts an design your own. :-)5 replies | 197 view(s)
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23rd January 2020, 12:18In my code I have a part where I am asserting a message at the Transcript window every 20us. Have added the flush() there. Works for me!3 replies | 232 view(s)
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23rd January 2020, 12:03dpaul replied to a thread Get some advice and tips to design ETHERNET switch or even TSN switch on FPGA in PLD, SPLD, GAL, CPLD, FPGA DesignIf you are using a Xilinx FPGA, I can advice you to use the TEMAC IP core (free hardware eval license) for initial understanding. Download and skim...5 replies | 197 view(s)
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23rd January 2020, 09:26You are apparently misunderstanding things. The WiFi adapters have two antenna ports for diversity purposes, each coax cable will be connected to a...1 replies | 98 view(s)
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22nd January 2020, 19:251. You can verify by checking the loop gain. 2. Choose initial conditions that result in a start magnitude below steady state. You'll see a rising...9 replies | 402 view(s)
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22nd January 2020, 16:10As explained by cariban, C1 and L1 aren't directly related, respectively there's no formula linking the values. For L1, I would use a low current...9 replies | 296 view(s)
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22nd January 2020, 15:11FvM replied to a thread Remove glitches in output frequency of ring oscillator in Elementary Electronic QuestionsWhat we see in post #1 is not jitter. It's an unstable oscillation mode. Apart from the question it's a real hardware effect or a simulation...10 replies | 423 view(s)
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22nd January 2020, 14:21Why 4.7 uF, why not 47 nF or 470 nF? You didn't yet specify any application parameters.9 replies | 296 view(s)
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22nd January 2020, 14:11FvM replied to a thread [SOLVED] LoopGain analysis with multiple feedback loop in Analog Circuit DesignSure, due to series-shunt feedback working.17 replies | 806 view(s)
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22nd January 2020, 14:09Looking at the *_simulation.log I found the following... # ** Fatal: (vsim-4) ****** Memory allocation failure. ***** # Attempting to allocate...3 replies | 232 view(s)
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22nd January 2020, 11:59I am using the Modelsim Microsemi Pro 2019.2. In the testbench I am opening a file in write mode and periodically writing data to it. I open the...3 replies | 232 view(s)
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22nd January 2020, 11:33FvM replied to a thread LLC converter vs Dual cascaded Buck….1000V to 48V at 500W output…no isolation needed in Power ElectronicsThe current spikes are caused by D3 snap-off. The diode is completely useless.18 replies | 469 view(s)
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22nd January 2020, 11:11Yes, that's what Easy peasy suggested.6 replies | 205 view(s)
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22nd January 2020, 09:33Using the winding only to power the feedback opto coupler doesn't make sense. But I presume you can read schematics good enough to see that the...6 replies | 205 view(s)
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22nd January 2020, 09:26No. MAC and PHY must be designed for 10 Gbps. 10GBASE-T (10 GBPS ethernet over RJ45 cables) hardware is yet expensive. Unlikely to be found in a...1 replies | 232 view(s)
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22nd January 2020, 08:56It depends. On the interference frequencies to be filtered, the device power, etc. C1 47nF up to several µF L1 is sketched as a common mode...9 replies | 296 view(s)
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22nd January 2020, 00:10FvM replied to a thread Remove glitches in output frequency of ring oscillator in Elementary Electronic QuestionsIt's usually expected that a RO oscillates at the lowest possible frequency with a period equal to twice the gate chain delay, without a frequency...10 replies | 423 view(s)
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21st January 2020, 23:52You know what the load impedance is, we can't determine if the lower driver impedance is actually necessary.6 replies | 291 view(s)
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21st January 2020, 15:50FvM replied to a thread How can I measure the Side-Band Amplitude? in RF, Microwave, Antennas and OpticsYou can either calculate the side band to carrier magnitude ratio based on the used modulation index or measure the magnitudes with a spectrum...3 replies | 267 view(s)
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21st January 2020, 15:33You might look for newer 18FxxKyy series that can achieve 64 MHz clock with internal oscillator and PLL. They support 115k or even higher baud rates....8 replies | 311 view(s)
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21st January 2020, 09:50FvM replied to a thread AVR Soft-Core (ATMega103) - issues during synthesis and implementation in PLD, SPLD, GAL, CPLD, FPGA DesignNo good suggestion, IMHO. I'd stay with forum rules in this regard: The idea is to keep the question context and support forum clearness. I...17 replies | 1345 view(s)
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21st January 2020, 09:33dpaul replied to a thread AVR Soft-Core (ATMega103) - issues during synthesis and implementation in PLD, SPLD, GAL, CPLD, FPGA DesignAn advice.... You can assemble your experience and later create a "Blog Entry" in this forum. Better than updating a thread.... Creating...17 replies | 1345 view(s)
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21st January 2020, 09:30FvM replied to a thread [SOLVED] LoopGain analysis with multiple feedback loop in Analog Circuit DesignMany possible reasons. It's useless to guess about it without the actual simulation circuit and component models.17 replies | 806 view(s)
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