FvM
Super Moderator
Find latest posts
View Articles
View Blog EntriesMini Statistics
- Join Date
- 22nd January 2008
- Last Activity
- Today 18:30
- Blog Entries
- 0
More 7 Friends
1 Groups
Join Groups 0 Permission Groups
FvM is not a member of any public groups
Awards
1st Helpful MemberAchievements
7 years registeredRecent Visitors
- Anomis,
- codemaster11,
- Dan1138,
- keroro1994,
- mahesXtremeEngineering,
- MILIND_7,
- Programmer.C,
- vimalraj,
- wizard,
- wondrous
- Tab Content
- FvM's Activity
- About Me
- Friends
- Experience
-
Older Activity
-
Today, 18:30If it's dimmable LED, what's the specification? Typically they use trailing edge phase control.23 replies | 382 view(s) -
Today, 14:08You can alternatively drive the 555 charge/discharge resistors by OUT pin, leaving DIS pin unconnected. Some flickering can be expected due to 500...23 replies | 382 view(s)
-
Today, 12:39It doesn't actually matter in this case, but your gate drive power calculation is completely wrong. Neither gate Iavg nor Irms is significant,...23 replies | 382 view(s)
-
Today, 11:49If you perform only 1 measurement per second, 40 µs division time (0.004 %) would be absolutely no issue. But I guess 1 Hz is too slow. For...7 replies | 230 view(s)
-
Today, 11:19I haven't yet found a differential probe that is suitable for measuring high side gate voltage without huge common mode crosstalk. I didn't yet check...5 replies | 146 view(s)
-
Yesterday, 19:59For the said measurement application (high side gate voltage), you need really high CMRR and a probe design that doesn't send common mode currents...5 replies | 146 view(s)
-
Yesterday, 14:07dpaul replied to a thread Interface Logic Model in Synosys is obsolete in ASIC Design Methodologies and Tools (Digital)What does the command reference manual say? Have you looked there?1 replies | 208 view(s) -
Yesterday, 14:02dpaul replied to a thread Get some advice and tips to design ETHERNET switch or even TSN switch on FPGA in PLD, SPLD, GAL, CPLD, FPGA DesignI know that and assumed the OP knows the difference. If he is a beginner in this area, it makes more sense for him to 1st understand how Ethernet...5 replies | 231 view(s)
-
Yesterday, 11:04I agree about using RS-422 or RS-485. It can work over many km in a party line topology with correct end termination. I'm however surprised that...11 replies | 385 view(s)
-
Yesterday, 10:36What's the opto triac type? I suggest an RCR filter/snubber circuit like below to prevent parasitic triggering. R2 can be reduced to 50 to 200 ohm...5 replies | 191 view(s)
-
23rd January 2020, 23:59Suggest you get self-triggering of opto triac or main triac by high dv/dt. That's likely to happen with inductive load, RC filters for the opto...5 replies | 191 view(s)
-
23rd January 2020, 17:17FvM replied to a thread Configuring ICE40 FPGA directly from ESP32 uC rather than using dedicated flash IC in PLD, SPLD, GAL, CPLD, FPGA Design"Slave SPI mode" in the configuration manual refers to operating the uC as SPI master and ICE40 as slave which is most likely the easier way.7 replies | 265 view(s)
-
23rd January 2020, 16:07dpaul replied to a thread Get some advice and tips to design ETHERNET switch or even TSN switch on FPGA in PLD, SPLD, GAL, CPLD, FPGA DesignYou need the understand the concepts an design your own. :-)5 replies | 231 view(s)
-
23rd January 2020, 12:18In my code I have a part where I am asserting a message at the Transcript window every 20us. Have added the flush() there. Works for me!3 replies | 242 view(s)
-
23rd January 2020, 12:03dpaul replied to a thread Get some advice and tips to design ETHERNET switch or even TSN switch on FPGA in PLD, SPLD, GAL, CPLD, FPGA DesignIf you are using a Xilinx FPGA, I can advice you to use the TEMAC IP core (free hardware eval license) for initial understanding. Download and skim...5 replies | 231 view(s)
-
23rd January 2020, 09:26You are apparently misunderstanding things. The WiFi adapters have two antenna ports for diversity purposes, each coax cable will be connected to a...1 replies | 108 view(s)
-
22nd January 2020, 19:251. You can verify by checking the loop gain. 2. Choose initial conditions that result in a start magnitude below steady state. You'll see a rising...9 replies | 412 view(s)
-
22nd January 2020, 16:10As explained by cariban, C1 and L1 aren't directly related, respectively there's no formula linking the values. For L1, I would use a low current...9 replies | 364 view(s)
-
22nd January 2020, 15:11FvM replied to a thread Remove glitches in output frequency of ring oscillator in Elementary Electronic QuestionsWhat we see in post #1 is not jitter. It's an unstable oscillation mode. Apart from the question it's a real hardware effect or a simulation...10 replies | 430 view(s)
-
22nd January 2020, 14:21Why 4.7 uF, why not 47 nF or 470 nF? You didn't yet specify any application parameters.9 replies | 364 view(s)
-
22nd January 2020, 14:11FvM replied to a thread [SOLVED] LoopGain analysis with multiple feedback loop in Analog Circuit DesignSure, due to series-shunt feedback working.17 replies | 846 view(s)
-
22nd January 2020, 14:09Looking at the *_simulation.log I found the following... # ** Fatal: (vsim-4) ****** Memory allocation failure. ***** # Attempting to allocate...3 replies | 242 view(s)
-
22nd January 2020, 11:59I am using the Modelsim Microsemi Pro 2019.2. In the testbench I am opening a file in write mode and periodically writing data to it. I open the...3 replies | 242 view(s)
-
22nd January 2020, 11:33FvM replied to a thread LLC converter vs Dual cascaded Buck….1000V to 48V at 500W output…no isolation needed in Power ElectronicsThe current spikes are caused by D3 snap-off. The diode is completely useless.18 replies | 498 view(s)
-
22nd January 2020, 11:11Yes, that's what Easy peasy suggested.6 replies | 214 view(s)
-
22nd January 2020, 09:33Using the winding only to power the feedback opto coupler doesn't make sense. But I presume you can read schematics good enough to see that the...6 replies | 214 view(s)
-
22nd January 2020, 09:26No. MAC and PHY must be designed for 10 Gbps. 10GBASE-T (10 GBPS ethernet over RJ45 cables) hardware is yet expensive. Unlikely to be found in a...1 replies | 281 view(s)
-
22nd January 2020, 08:56It depends. On the interference frequencies to be filtered, the device power, etc. C1 47nF up to several µF L1 is sketched as a common mode...9 replies | 364 view(s)
-
22nd January 2020, 00:10FvM replied to a thread Remove glitches in output frequency of ring oscillator in Elementary Electronic QuestionsIt's usually expected that a RO oscillates at the lowest possible frequency with a period equal to twice the gate chain delay, without a frequency...10 replies | 430 view(s)
-
21st January 2020, 23:52You know what the load impedance is, we can't determine if the lower driver impedance is actually necessary.7 replies | 309 view(s)
About FvM
Basic Information
Optional Info
- Location:
- Bochum, Germany
- Interests:
- Analog, DSP, Power electronics and more
Statistics
Total Posts
- Total Posts
- 46,045
- Posts Per Day
- 10.50
General Information
- Last Activity
- Today 18:30
- Join Date
- 22nd January 2008
Helpful Postings
- Has Rated
- 2127
- Post Rated
- Rated helpful 13651 out of 13651 times
7 Friends
Showing Friends 1 to 7 of 7
Experience
Points
- Points
- 263,518
- Level
- 100
Level up completed
- Level up completed
- 0%
- Points required
- 0
Activity
- Activity
- 100.0%
- Activity last 30 days
- 100.0%
- Activity last 7 days
- 100.0%
Points
All Points for user
- Points for User
- 58,869
- Points for Reputation
- 54,102
- Points for every day since registration
- 4,737
- Points for Friends
- 24
- Points for posting Visitormessages
- 2
- Points for filling profile
- 4
All Points for threads
- Points for threads
- 4,053
- Points for Threads
- 113
- Points for tagging threads
- 3,815
- Points for replies
- 125
All Points for posts
- Points for Posts
- 200,595
- Points for Posts
- 132,206
- Points for uploading Attachments
- 54
- Average Posts per Day
- 9.00
- Helpful Answers
- 68,335
All Points for miscellaneous
- Points for Misc
- 0
Activities
25th January 2020
- 03:05 FvM has earned 2 Points for User points
- 03:05 FvM has earned 14 Points for Posts points
24th January 2020
- 03:05 FvM has earned 3 Points for User points
- 03:05 FvM has earned 14 Points for Posts points
- 03:05 FvM has earned 1 Points for threads points
23rd January 2020
- 03:05 FvM has earned 6 Points for User points
- 03:05 FvM has earned 45 Points for Posts points
- 03:05 FvM has earned 1 Points for threads points
22nd January 2020
- 03:05 FvM has earned 3 Points for User points
- 03:05 FvM has earned 26 Points for Posts points
- 03:05 FvM has earned 2 Points for threads points
21st January 2020
- 03:06 FvM has earned 4 Points for User points
- 03:06 FvM has earned 37 Points for Posts points
- 03:06 FvM has earned 2 Points for threads points
20th January 2020
- 03:05 FvM has earned 5 Points for User points
- 03:05 FvM has earned 22 Points for Posts points
- 03:05 FvM has earned 2 Points for threads points
19th January 2020
- 03:05 FvM has lost -355 Points for User points
- 03:05 FvM has earned 38 Points for Posts points
- 03:05 FvM has earned 2 Points for threads points
Show Activities from all Users