FvM
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Yesterday, 23:26You want to read the class specification documents. CDC and HID don't use all transfer types, e.g not isochronous. CDC implies control, interrupt and...2 replies | 115 view(s) -
Yesterday, 23:00No damage, but also no high voltage output. Primary fly-back voltage needs to go up to 600V for 50000V secondary.6 replies | 189 view(s)
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Yesterday, 10:30FvM replied to a thread Flyback SMPS power MOSFET getting hot? uc3843 pwm converter in Power ElectronicsRCD snubber is the appropriate method to absorb primary overvoltage caused by transformer leakage inductance. You have to check the actual primary...24 replies | 772 view(s)
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Yesterday, 10:19Think about an ADC with DMA support and USB high speed or 100 Mbit Ethernet interface. Suitable CPUs are e.g. PIC32 (new MZ family has USB HS) or ARM...6 replies | 209 view(s)
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Yesterday, 10:08Back emf is is causing the ignition spark (fly-back converter principle), you don't want to cut it.6 replies | 189 view(s)
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Yesterday, 09:45FvM replied to a thread Phase Difference calculation in cadence. in RF, Microwave, Antennas and OpticsWhat's the actual problem? Verification of your "phase shifter" or designing a phase or flight time measurement system? Does your "phase shifter"...3 replies | 129 view(s)
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Yesterday, 09:25FvM replied to a thread Runtime of clock using alkaline D cells instead of AA batteries in Elementary Electronic QuestionsDoesn't this demand for a transformer supply with battery backup? The battery is only discharged during power failure then.11 replies | 196 view(s)
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Yesterday, 09:17Means 16A resistive, 4A inductive load.3 replies | 96 view(s)
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Yesterday, 09:02FvM replied to a thread Relay selection for Ultrasonic signals in RF, Microwave, Antennas and OpticsI don't see a necessity to use GHz relays for 25 MHz signal. I would probably select a slightly bigger relays with higher contact breakdown voltage....4 replies | 150 view(s)
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20th September 2019, 16:35You can design FIR filters in Matlab and import the filter coefficients to the Intel FIR compiler tool. Lock-in is a different approach involving...3 replies | 148 view(s)
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20th September 2019, 16:23SATA A/B assignment on the M2 connector should be according to the usage with standard SATA connector.1 replies | 100 view(s)
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20th September 2019, 16:03If the measurements are correct, a large share of the primary current runs as magnetizing current into the transformer inductance. You only told...36 replies | 1991 view(s)
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19th September 2019, 15:44Good idea. I guess you have input or output AC coupling and the bias point is shifting when the input signal is rectified in saturated operation.3 replies | 136 view(s)
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19th September 2019, 08:54FvM replied to a thread How good is ultiboard? in PCB Routing Schematic Layout software and SimulationFirstly I'd like to hint to a sticky thread on top of this forum...3 replies | 181 view(s)
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19th September 2019, 08:02FvM replied to a thread Power harvester evaluation board and antenna issues in Elementary Electronic QuestionsAre you serious? Using an amplifier with energy harvesting? Did you understand the basic idea? - - - Updated - - - Energy harvesting is...2 replies | 101 view(s)
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18th September 2019, 16:42There may be good reasons to implement a linear (class AB) amplifier for your purposes, I don't apply to decide yes or no. You have implicitly...12 replies | 444 view(s)
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18th September 2019, 12:21FvM replied to a thread In distributed amplifiers, is it total input capacitance of the gain stage or Cgs in RF, Microwave, Antennas and OpticsSeriously, does the discussion about terms help in any way to answer the original question? Does the term "artificial transmission line" clarify...4 replies | 295 view(s)
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18th September 2019, 11:49The swing example is inappropriate for the original gyroscope problem. Swing involves periodical transfer between potential and kinetic energy. Work...50 replies | 1324 view(s)
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18th September 2019, 10:50dpaul replied to a thread How do i read or write to ram address given in datasheet? using verilog in PLD, SPLD, GAL, CPLD, FPGA DesignAs mentioned above, you need to provide the bus info connecting the RAM. Then you need to drive those bus signals for READ or WRITE cases.2 replies | 152 view(s) -
18th September 2019, 08:19Doesn't sound bad in general, but some details aren't quite clear. Do you mind to share a CAD drawing of the intended sensor mount?1 replies | 217 view(s)
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17th September 2019, 22:02FvM replied to a thread Operational amplifier driving capability test in Analog Integrated Circuit (IC) Design, Layout and FabricationThe described setup (setting a fixed output voltage) doesn't fully test "driving capability", you want to evaluate the available output current over...11 replies | 264 view(s)
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17th September 2019, 18:33FvM replied to a thread Problem adding reset to master slave D-FF for phase detector in ASIC Design Methodologies and Tools (Digital)In a regular master slave FF, the asynchronous reset signal is expected to immediately reset both stages independent of the clock state, that's what...5 replies | 326 view(s)
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17th September 2019, 16:03Individual harmonics have different limit values. THD isn't enough. As for the general question, FFT is supported by most modern digital scopes....11 replies | 823 view(s)
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17th September 2019, 09:54FvM replied to a thread Higher Current Consumption than expected with AFE and embedded Flash in IoT - Internet of ThingsHard to give less information… Where do you see the current peak and when? You should be able to trace the current path down to the component...6 replies | 205 view(s)
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17th September 2019, 09:31FvM replied to a thread [SOLVED] Suppressing the spacing in $fwrite command of Verilog in PLD, SPLD, GAL, CPLD, FPGA DesignReview System Verilog language reference, paragraph 21.2.1.3 Size of displayed data. It's regular C format specifier syntax, by the way.3 replies | 155 view(s)
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16th September 2019, 16:24It depends. Some thermal pastes with high thermal conductivity are metal filled and also electrically conductive. But as far as I can see from the...26 replies | 824 view(s)
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16th September 2019, 13:58FvM replied to a thread [SOLVED] AMS simulation of D-FF in Analog Integrated Circuit (IC) Design, Layout and FabricationThere's no clock signal fed to your circuit, respectively output is uninitialized.. Confusingly you are providing a multi level ("electrical")...2 replies | 163 view(s)
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16th September 2019, 12:59The order of magnitude sounds reasonable. Obviously the numbers have been empirically validated, but your antenna geometry may be different. You...8 replies | 428 view(s)
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