FvM
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Today, 09:33FvM replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA DesignA bit more complex. You'll design a kind of software PLL with 2 and 4 MHz output, locked to the 2 MHz reference. Dynamic phase shift might be used if...11 replies | 431 view(s) -
Today, 09:21High Voltage Coupling means what, exactly? Measuring current, voltage, linearly, which range? HCPL-0370 reference suggest you want to compare current...2 replies | 53 view(s)
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Yesterday, 22:36If you experience contradicting hearsay specs, why not refer to major manufacturers datasheets instead?4 replies | 143 view(s)
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Yesterday, 22:20I believe, you either don't read the answers or don't understand it. I have no other explanation for seeing the circuit in post #45 that has been...48 replies | 973 view(s)
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Yesterday, 13:39Incomplete problem description results in ambiguous or useless answer. At least one unclear point is floating substrate nodes. Transconductance...3 replies | 172 view(s)
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Yesterday, 13:181/2 sample period is no meaningful quantity in sampled data system. Output is only observed at integer multiples of sampling period. You'll see if...2 replies | 97 view(s)
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Yesterday, 13:01A symmetrical fault example, referring to your previous design. How would you detect it? - - - Updated - - - The file is different from...19 replies | 497 view(s)
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Yesterday, 12:47I feel that some points should be sorted out. You have been originally asking how to amplify µV signal to mV, with minimal supply voltage. Later...48 replies | 973 view(s)
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Yesterday, 11:34The idea of an ungrounded network (IT network) is to avoid short circuit currents in case of a single ground fault while being able to detect the...19 replies | 497 view(s)
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Yesterday, 10:26A RHP pole in the open loop transfer function can be only generated if the feedforward turns into positive feedback, likely to happen for the post #1...3 replies | 176 view(s)
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15th February 2020, 12:58FvM replied to a thread Waveform saving upon trigger in windows from Oscilloscope in Elementary Electronic QuestionsMSO2000B series has 1M data points memory, about 10 sec @ 100 kSPS. Timebase can be set up to 100 s/div, 1000 s total length with respective lower...5 replies | 238 view(s)
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15th February 2020, 12:15Your monitor circuit is generating huge leakage currents and power dissipation and surely no acceptable IMD solution. What is your of insulation...19 replies | 497 view(s)
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15th February 2020, 11:39FvM replied to a thread Waveform saving upon trigger in windows from Oscilloscope in Elementary Electronic QuestionsThe simple way to save the waveform is to set up acquisition parameters as required, make a measurement and save the waveform to USB drive in *.csv...5 replies | 238 view(s)
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14th February 2020, 15:45In case you want someone to check your transformer design, you should give complete information, e.g. which input voltage was used during the test....21 replies | 475 view(s)
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14th February 2020, 15:32Inrush current can be captured with a current probe and a digital oscilloscope. It's not clear what you exactly want to achieve and how the...3 replies | 186 view(s)
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14th February 2020, 09:48FvM replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA DesignPossible solutions have been sketched, but the application requirements are yet unknown.11 replies | 431 view(s)
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14th February 2020, 09:42IMD (insulation monitoring devices) are specified by IEC 61557 and available on the market. For unearthed (IT) power supplies, these devices are...19 replies | 497 view(s)
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14th February 2020, 09:27dpaul replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA DesignThe OP has posted the same Q in Xilinx forums yesterday and did not provide sufficient details in order to answer his Q. My answer to him would be...11 replies | 431 view(s) -
14th February 2020, 09:00FvM replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA Design10 MHz minimal clock input frequency is common series 7 MMCM spec as far as I'm aware of.11 replies | 431 view(s)
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13th February 2020, 18:08FvM replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA DesignIf you have a higher frequency clock available, a digital PLL can generate the 4 MHz clock, however limited to the time resolution of the system...11 replies | 431 view(s)
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13th February 2020, 17:25Having already multi mV range offset: surely not.48 replies | 973 view(s)
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13th February 2020, 17:21FvM replied to a thread Gas flow meter + Gas pressure meter + Vacuum meter? in Analog Circuit Design2. There's no simple method to add a readout to float-type flowmeter (rotameter). Most economic flow meters (I doubt you find cheap sensors with...2 replies | 189 view(s)
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13th February 2020, 09:02Literally, a VCO is a VFC (voltage to frequency converter) and vice versa. Specifically the term VFC refers to converters with large frequency ratio...9 replies | 552 view(s)
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13th February 2020, 08:52Some key specs missing: Signal bandwidth, source impedance, acceptable noise level (specified as voltage density or wideband noise level, e.g. 0.1 to...48 replies | 973 view(s)
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13th February 2020, 08:42I understand this as a mostly theoretical question. On the application layer, you don't select frequencies in Bluetooth, this is done by the...3 replies | 262 view(s)
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12th February 2020, 22:42FvM replied to a thread [SOLVED] Simple Model of Lithium-Ion Battery (PSpice) in Elementary Electronic QuestionsDid you review the li-ion models at https://groups.io/g/LTspice4 replies | 212 view(s)
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12th February 2020, 22:34FvM replied to a thread Plane filled with copper/ground plane on one single PCB layer in Elementary Electronic QuestionsWhy do you assume that copper pours are not connected to ground and don't perform an electrical function? A ground area, broken by components and...14 replies | 409 view(s)
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12th February 2020, 17:35Do you mean high speed according to the USB spec, 480 MBPS? It requires dedicated PHY hardware which isn't available inside a FPGA. The intended...10 replies | 572 view(s)
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12th February 2020, 17:19Review your Verilog-A reference for absdelay() statement.3 replies | 245 view(s)
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11th February 2020, 23:44FvM replied to a thread Old capacitor needs replacing not sure what to replace with. in Hobby Circuits and Small Projects ProblemsAs explained in post #11, the capacitance of the Y capcitor shouldn't be larger than 5 nF to avoid too high ground leakage current.15 replies | 824 view(s)
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