FvM
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Today, 18:07The counter design is likely to cause irregular behavior by using asynchronous reset. Now, as you have moved everything to a single clock domain, all...14 replies | 206 view(s) -
Today, 17:02FvM replied to a thread How to implement a transfer function with discrete components in Analog Circuit DesignO.K., just an exercise. As you see, it can be implemented. There are however additional problems related to input signal level and OP voltage...22 replies | 603 view(s)
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Today, 16:51FvM replied to a thread [SOLVED] Help to translate verilog code lines to vhdl in PLD, SPLD, GAL, CPLD, FPGA DesignYes you created a new topic, but according forum rules it's not appropriate, they say That's clearly a related question, without the original...9 replies | 141 view(s)
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Today, 15:39FvM replied to a thread Embedded project needs devices which can work continuously at +125 degree C in MicrocontrollersThat's how SPI bus works. Review the interface description in datasheet, SO has internal tri-state driver enabled by CS.68 replies | 1817 view(s)
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Today, 15:33FvM replied to a thread [SOLVED] Help to translate verilog code lines to vhdl in PLD, SPLD, GAL, CPLD, FPGA DesignThe definition of wbus_count doesn't make sense, it must be two-dimensional to make the assignment work. Presently RHS is std_logic and LHS 10 bit...9 replies | 141 view(s)
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Today, 15:14The estimation is valid for first order low-pass respectively system with dominant pole. To keep 500 ps rise time of a band limited input signal, the...4 replies | 64 view(s)
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Today, 14:57More or less. There's no typical Vf specification in the datasheet, only maximal. Seeing actually about 1V Vf at 0.1A is a bit surprising, but yes,...3 replies | 58 view(s)
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Today, 14:47Some can be probably used. The specification is however incomplete: - DC capable amplifier yes/no - gain respectively output level -...4 replies | 64 view(s)
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Today, 12:51With only 150 Hz bandwidth, there's absolutely no advantage in using fully differential signaling between amplifier and DAQ board. Instead you can...3 replies | 104 view(s)
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Today, 12:41FvM replied to a thread Where to find Altera PLDShell v5.0 Software in PLD, SPLD, GAL, CPLD, FPGA DesignI rather thought, support has ended at least 10 years ago... As far as I'm aware of, EP300 series is compatible to industry standard PAL/GAL...3 replies | 133 view(s)
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Today, 12:11You are describing the problem with inappropriate terminology. You are not "adding frequencies", you are combining signals. Combining signals...3 replies | 124 view(s)
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Today, 10:01Single phase synchronous motors usually have low starting torque. It might be that the motor isn't suited for your application. Motors with run...3 replies | 82 view(s)
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Today, 09:37The most simple solution is to use synchronizer logic that generates a clock enable pulse in the 40 MHz domain for each rising edge of rf_in and...14 replies | 206 view(s)
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Today, 09:20FvM replied to a thread VHDL code flow in ISE Design Suite 14.7 in PLD, SPLD, GAL, CPLD, FPGA DesignReviewing your code can help. Look at the integer range definition of divrel1. Range of 0 to 1500 is implemented as 11 bit unsigned in synthesis,...3 replies | 66 view(s)
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Today, 07:50FvM replied to a thread How to implement a transfer function with discrete components in Analog Circuit DesignSee comparison of standard all-pass and unequal (lhp)pole/zero circuits Not possible with simple discrete circuit. Applies either to...22 replies | 603 view(s)
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Yesterday, 23:57FvM replied to a thread Help needed to reduce Harmonics from a firing angle control circuit in Power ElectronicsPower quality regulations (e.g. IEC 61000-3-2) don't allow phase angle control for heating applications, only for lighting control. Full wave...2 replies | 101 view(s)
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Yesterday, 17:35The short answer is that you get zero result because the frequency counter is reset before you latch the value, as already explained by ads-ee. ...14 replies | 206 view(s)
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Yesterday, 14:35dpaul replied to a thread Where to find Altera PLDShell v5.0 Software in PLD, SPLD, GAL, CPLD, FPGA DesignAltera is now Intel. So have you checked Intel website for Alters's antiquated software.3 replies | 133 view(s) -
Yesterday, 14:08dpaul replied to a thread How to begin development on SOC (xilinx) in PLD, SPLD, GAL, CPLD, FPGA Design1. Depending upon the simu, synth & PnR tools you are using, TCL can become handy. 2. The cost of a Xilinx FPGA based dev board will depend on the...3 replies | 120 view(s)
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Yesterday, 12:42It's possible to change the RC servo setpoint immediately from left to right stop. Question is if the connected hardware likes it. Also the servo...3 replies | 150 view(s)
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Yesterday, 09:35Yes, divrel is the servo set point. Every thing else in the code should be kept.3 replies | 150 view(s)
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Yesterday, 09:28FvM replied to a thread [SOLVED] Value of resistance and impedance in Elementary Electronic QuestionsConsidering that the skin resistance varies by several orders of magnitude depending on various conditions, the discussed 20% variation is almost...4 replies | 154 view(s)
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Yesterday, 00:09FvM replied to a thread How to implement a transfer function with discrete components in Analog Circuit Design1. Know that a RHPZ + single pole combo with unequal pole/zero frequencies can be implemented by modification of a standard active all-pass 2. Add a...22 replies | 603 view(s)
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17th February 2019, 23:55No. Light dimmers implement phase angle control and cut part of the sinusoidal mains waveform without changing the frequency. Variable frequency...12 replies | 422 view(s)
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17th February 2019, 22:58FvM replied to a thread [SOLVED] Potentiostatic circuit operation and ADC interface in Analog Circuit DesignMost of the circuit is pretty standard electrochemical sensor processing, but the counter electrode measurement is a bit unusual. I guess it's for...2 replies | 104 view(s)
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17th February 2019, 16:44FvM replied to a thread Low and High Frequnecy Response in Analog Integrated Circuit (IC) Design, Layout and FabricationO.K., I understand what you mean. fH obtained from the said "open circuit time constant" method is an estimation of the upper 3 dB corner. It's a...11 replies | 352 view(s)
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17th February 2019, 12:14FvM replied to a thread Turn on/off hall light with presence detection in Elementary Electronic QuestionsPossibly. You should specify the requirements clearly. From what I have understood so far, you are asking for a long range (> 1m range) RFID system,...3 replies | 131 view(s)
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