FvM
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Today, 21:57Next step is to make informative measurements, e.g. oscilloscope waveforms.4 replies | 275 view(s) -
Today, 18:23I would assume that the code is executed out of the flash memory rather moved to RAM. In this case, the RAM #WR signal won't be pulled low before a...4 replies | 90 view(s)
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Today, 08:51FvM replied to a thread can triacs rapidly switch AC into a transformer in Elementary Electronic QuestionsGate driver should be of course referenced to common source node. There are several reasons why the "chopper" circuit can't be used in the shown...7 replies | 160 view(s)
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Yesterday, 13:00Perhaps we can paraphrase the question: Is it reasonable to start system level microcontroller programming without studying the datasheet...2 replies | 100 view(s)
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Yesterday, 12:47I believe the question has been already answered by Akanimo. All externally connected IO pins, user clock, reset etc. must be present in the top...19 replies | 815 view(s)
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Yesterday, 07:43The PWM circuit makes no sense as drawn, please review. I guess the µC PWM output should be controlling the switch, not feeding a switch terminal. ...5 replies | 201 view(s)
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14th July 2019, 23:28I mean one multitap voltage divider instead of three. 3 kV/mm is a large multiple of the clearance values suggested by safety and PCB design...88 replies | 2109 view(s)
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14th July 2019, 23:00FvM replied to a thread Looking for SPICE model for coupled lossy transmission line in Electromagnetic Design and SimulationIf you want a S-parameter model, why are you asking for a SPICE model? A simple behavioral model with constant delay and sqrt(f) proportional losses...7 replies | 269 view(s)
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14th July 2019, 17:17Microchip doesn't use JTAG interface for debugging. Unlikely, it's 18 years old. I guess you mean MPLAB X IDE 5.10. #pragma config ICS =...5 replies | 181 view(s)
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14th July 2019, 15:13At least two problems: - still asymmetrical voltage divider by not switching the input side of the negative dividers - PCB clearance not suited for...88 replies | 2109 view(s)
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14th July 2019, 15:03FvM replied to a thread parasitic coil capacitance from frequency in Elementary Electronic QuestionsParasitic coil capacitance refers to parallel capacitance, I presume. Thus you are looking for the parallel resonance of the unloaded coil. The best...3 replies | 186 view(s)
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14th July 2019, 14:47FvM replied to a thread [SOLVED] impedance matching methods | ADS matching tool in RF, Microwave, Antennas and OpticsThe most simple solution to the exercise problem (match 220 ohm || 0.877 pf to 50 ohm in 1.2 to 1.8 GHz band) is a single series inductor of about...3 replies | 226 view(s)
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14th July 2019, 12:58Suggest to read the section 8.2 up to the posted snippet more thoroughly. Your questions are already answered in the text. Look from where they are...1 replies | 135 view(s)
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13th July 2019, 22:27FvM replied to a thread Inrush pulse in 0R56, 1206 resistor....gradual degradation? in Power ElectronicsWhat you name "scope shots" are simulation waveforms under probably unrealistic conditions. How about a simulation with realistic mains impedance?2 replies | 134 view(s)
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13th July 2019, 12:35FvM replied to a thread how to design a thermostat without Microcontroller? in Analog Circuit DesignUnfortunately we didn't yet see a complete schematic that comprises the various changes and supplements mentioned in the posts, including power...84 replies | 3497 view(s)
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13th July 2019, 11:37FvM replied to a thread copper pour in top layer with vcc net in PCB Routing Schematic Layout software and SimulationPosting the gerber files might clarify the problem. We have insufficient information yet. If the PCB is made with correct component definitions...7 replies | 339 view(s)
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13th July 2019, 11:28FvM replied to a thread [SOLVED] impedance matching methods | ADS matching tool in RF, Microwave, Antennas and OpticsI neither understand the proceeding in the document. Obviously the simple matching network at page 6 fulfills the requirements (|S11| < -9 dB) while...3 replies | 226 view(s)
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13th July 2019, 11:02I merged the two threads according to forum rules. "Ask related questions in one thread". The question has been basically answered by asdf44 in...19 replies | 815 view(s)
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13th July 2019, 10:46I don't recognize a differential probe circuit. Previous post #76 looks better. You have insufficient PCB clearance and the range switch is hardly...88 replies | 2109 view(s)
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13th July 2019, 09:10FvM replied to a thread Bypass dc signal which is accompanied with a low frequency sinusoidal signal in Analog Circuit DesignStrictly speaking you need large time constant, not necessarily large capacitor. You should talk about circuit impedance first. What's the load...4 replies | 203 view(s)
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13th July 2019, 08:32FvM replied to a thread parasitic coil capacitance from frequency in Elementary Electronic QuestionsCan't be answered without knowing the complete measurement circuit.3 replies | 186 view(s)
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12th July 2019, 09:42FvM replied to a thread Looking for SPICE model for coupled lossy transmission line in Electromagnetic Design and SimulationThe question is less clear than it may seem at first sight. You can easily make a LGRC lumped transmission line model, also coupled lines can be...7 replies | 269 view(s)
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11th July 2019, 21:40FvM replied to a thread dsPIC30F2010 - 30 I/SP restarts at interval of 20seconds for no known reason in MicrocontrollersBesides code review, you should also learn to read reset reason register.9 replies | 435 view(s)
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11th July 2019, 18:32FvM replied to a thread VHDL use of 'Z' std logic for bus, or should one use interconnect? in PLD, SPLD, GAL, CPLD, FPGA Design'Z' or 'X' isn't a detectable state in synthesized logic. Respectively Quartus synthesis tool assumes that 'Z' can't be sensed on input and...6 replies | 181 view(s)
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11th July 2019, 08:47dpaul replied to a thread Attempting to get a license for feature 'Synthesis' and/or device 'xcvu440' in PLD, SPLD, GAL, CPLD, FPGA DesignAdding the ads-ee comments from above.... Xilinx ISE is for Series6 and previous versions of FPGAs. If your target FPGA has changed, so should your...6 replies | 259 view(s) -
11th July 2019, 08:44dpaul replied to a thread Issues during attemp of implementation of "Matrix multiplification" Verolig project in PLD, SPLD, GAL, CPLD, FPGA DesignYes, use Core Generator to generate. Otherwise consult the Xilinx ISE Synthesis guide in which there probably are RTL templates which infer BRAM.3 replies | 177 view(s)
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10th July 2019, 23:10FvM replied to a thread Does it exist an AC to AC converter in small package for converting 220v to 110v? in Power ElectronicsToroid transformer is an option if you want a smaller solution, the OP might consider it or refer to a classical EI core design. It's also a good...24 replies | 642 view(s)
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