FvM -

Yesterday, 13:46

dpaul replied to a thread Transferring data from PS to PL in PLD, SPLD, GAL, CPLD, FPGA Design

see this thread on PS-PL communication - https://forums.xilinx.com/t5/Embedded-Processor-System-Design/PS-PL-communication/td-p/847775 You might...

6 replies | 170 view(s)

Yesterday, 10:24

dpaul replied to a thread Transferring data from PS to PL in PLD, SPLD, GAL, CPLD, FPGA Design

For PL to PS, you can also use the AXI i/f. The PS section can typically stay as the master and the PL section can stay as the AXI slave. The...

6 replies | 170 view(s)

Yesterday, 09:52

FvM replied to a thread Transferring data from PS to PL in PLD, SPLD, GAL, CPLD, FPGA Design

What is PL and PS? See forum rules, you shouldn't use

6 replies | 170 view(s)

Yesterday, 08:22

FvM replied to a thread Sine PWM calculated with pic, instead of using table in Microcontrollers

Regarding PWM scheme in post #19, it produces intended sine waveform only for resistive and under circumstances inductive load.

22 replies | 819 view(s)

Yesterday, 08:12

FvM replied to a thread Bridge Rectifier won't Rectify in Power Electronics

It really depends on the intended probe frequency range, which wasn't specified along this thread. The shown resistor divider primarily suffers from...

21 replies | 462 view(s)

18th August 2019, 22:56

FvM replied to a thread Pulse transformer output measured vs. calculated? in Power Electronics

O.k., voltage and current are almost in phase now, apparently a DC offset of the Rokowski measurements is causing a ramp in the current display,...

23 replies | 534 view(s)

18th August 2019, 11:31

FvM replied to a thread Pulse transformer output measured vs. calculated? in Power Electronics

With an estimated capacitance of 1 pF for the 100 Mohm resistor, you get a zero at 1600 Hz. A single 1 nF compensation capacitor can at least improve...

23 replies | 534 view(s)

18th August 2019, 10:41

FvM replied to a thread Pulse transformer output measured vs. calculated? in Power Electronics

Is it a similar divider as in your other thread? If so, I doubt that the voltage waveform isn't reproduced correctly. Similarly, what kind of...

23 replies | 534 view(s)

18th August 2019, 08:07

FvM replied to a thread Bridge Rectifier won't Rectify in Power Electronics

Rectifier output voltage is clamped to n*diode forward voltage, e.g. a few 10 V in your design.

21 replies | 462 view(s)

17th August 2019, 22:25

FvM replied to a thread Bridge Rectifier won't Rectify in Power Electronics

It's not surprizing to see large ripple at the rectifier output. Negative voltage as shown is however not feasible. Most likely explanation is the...

21 replies | 462 view(s)

17th August 2019, 14:10

FvM replied to a thread STM32F3 built-in opertion amplifier in Microcontrollers

You're simply confusing source and load impedances. Rain is the impedance of the source driving the ADC, minimal OP load impedance has nothing to do...

7 replies | 245 view(s)

17th August 2019, 13:55

FvM replied to a thread Why does my homemade Yagi wifi antenna perform so poorly? in RF, Microwave, Antennas and Optics

You are right, driving element impedance depends on the reflector and director spacing. I found this table in Balanis Antenna Theory. Numbers are for...

17 replies | 623 view(s)

16th August 2019, 22:35

FvM replied to a thread Center tapped transformer (forward converter) in Power Electronics

You can try to make the 12 V inductor large enough to provide continuous current at 2 W load. Coupled inductors can basically work, obviously the...

12 replies | 379 view(s)

16th August 2019, 22:30

FvM replied to a thread Why does my homemade Yagi wifi antenna perform so poorly? in RF, Microwave, Antennas and Optics

Thanks for mentioning the foam board. So it's actuality a folded dipole. Unfortunately it's seriously mismatched in this case, having typically 290...

17 replies | 623 view(s)

16th August 2019, 22:05

FvM replied to a thread Pulse transformer output measured vs. calculated? in Power Electronics

How do you measure it? Sure that the probes don't affect the circuit? The question isn't clear at all.

23 replies | 534 view(s)

16th August 2019, 15:27

dpaul replied to a thread verilog code using vivado in PLD, SPLD, GAL, CPLD, FPGA Design

Post the complete RTL. Are you properly doing the system clock input pin assignment in the xdc file?

3 replies | 142 view(s)

16th August 2019, 15:24

dpaul replied to a thread Verilog code for 8 bit register with read/write in PLD, SPLD, GAL, CPLD, FPGA Design

I hope you realize that in order to have data from an axi slave to a 8 bit register, the 8 bit register must also have an axi wrapper. That axi...

6 replies | 393 view(s)

16th August 2019, 11:22

FvM replied to a thread verilog code using vivado in PLD, SPLD, GAL, CPLD, FPGA Design

The post body doesn't match the title. Where's the Verilog code?

3 replies | 142 view(s)

16th August 2019, 11:13

FvM replied to a thread Why does my homemade Yagi wifi antenna perform so poorly? in RF, Microwave, Antennas and Optics

As shown in the picture, it's a straight 60 to 75 ohm half wave dipole, not a folded dipole. This makes sense because it's roughly matched to the 50...

17 replies | 623 view(s)

16th August 2019, 10:58

FvM replied to a thread Center tapped transformer (forward converter) in Power Electronics

Apart from possible ringing and overshoot, a forward converter shows only tracking outputs if both inductors are in continuous conducting mode (CCM)....

12 replies | 379 view(s)

15th August 2019, 12:26

FvM replied to a thread [SOLVED] magnet wire parasitic properties in Elementary Electronic Questions

Self capacitance in the Snelling book means inter turn capacitance.

5 replies | 236 view(s)

15th August 2019, 10:01

FvM replied to a thread Master slave connection in Analog Circuit Design

If it's isolated RS-485, e.g. PROFIBUS network, it doesn't necessarily use ground connection. Star connection through "junctions box" is only...

4 replies | 175 view(s)

15th August 2019, 09:51

FvM replied to a thread [SOLVED] magnet wire parasitic properties in Elementary Electronic Questions

Snelling, Soft Ferrites, paragraph 11.6 The Self Capacitance of a Winding does detail calculations of different winding configurations. The 1969...

5 replies | 236 view(s)

15th August 2019, 08:05

dpaul replied to a thread Embedded Linux Application in PLD, SPLD, GAL, CPLD, FPGA Design

For Xilinx FPGAs containing ARM core/s I can recommend you to start with the this free to download eBook: http://www.zynqbook.com/ Many of the...

2 replies | 182 view(s)

14th August 2019, 22:37

FvM replied to a thread 1 minute vs 1 second isolation voltage test for isolated offline SMPS transformer in Power Electronics

You have previously written that the power supply is classified as basic insulation. Then the test is surely not performed with 3750 VAC. EN 61558 is...

17 replies | 735 view(s)

14th August 2019, 15:51

dpaul replied to a thread [SOLVED] Modelsim clock signal in PLD, SPLD, GAL, CPLD, FPGA Design

I would never use stuff as create_wave or try to force a toggle behavior in order to generate a fundamental signal such as clock. For signals such...

10 replies | 385 view(s)

14th August 2019, 13:52

FvM replied to a thread AD8428 Comon mode issue(?) in Analog Circuit Design

I presume 0.2V additional output offset doesn't overload the ADC range. How about a 2-point correction (y = ax + b) of offset and scaling error...

6 replies | 254 view(s)