FvM
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Yesterday, 22:21Did you try to detetmine the loss components yourself? The quoted statement can't be found in the datasheet. "Loss due to parasitic leakage...4 replies | 129 view(s) -
Yesterday, 08:40FvM replied to a thread Voltage to frequency conversion using VFC32 in Elementary Electronic QuestionsWhy now? What did you change? µF? Really?7 replies | 359 view(s)
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13th October 2019, 21:13FvM replied to a thread Will the TVS diode protect the DC line from AC power? in Elementary Electronic QuestionsPresume you have read the SMBJ5 datasheet, particularly about limiting voltage. Presumed you have a current limiting element that can withstand 230V...2 replies | 162 view(s)
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13th October 2019, 20:35FvM replied to a thread Which transformers can pass approvals testing rergarding isolation voltage testing? in Power ElectronicsIt's necessary to design the transformer with sufficient clearance in this place. By the way, what's the safety specification (overvoltage category,...7 replies | 232 view(s)
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13th October 2019, 18:24FvM replied to a thread Which transformers can pass approvals testing rergarding isolation voltage testing? in Power ElectronicsDid you design the transformer yourself? What's the clearance between primary windings and secondary terminals? If it's actually an isolation failure...7 replies | 232 view(s)
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13th October 2019, 18:07FvM replied to a thread Output of Nand Sequential based Phase-Frequency Detector in Analog Integrated Circuit (IC) Design, Layout and FabricationYou didn't report the transistor technology. I presume you can see how the intermediate level is achieved if you look at all voltage. I guess it's...1 replies | 141 view(s)
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13th October 2019, 17:53FvM replied to a thread question about Friis equation with very large antenna gain in RF, Microwave, Antennas and OpticsFriis equation is valid for far field. Most likely you are still in the near field range if your example achieves positive power gain. Or the assumed...2 replies | 144 view(s)
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13th October 2019, 08:27Post #1 describes the basic CAN operation correctly.3 replies | 285 view(s)
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13th October 2019, 08:15Patience! People are taking part in the forum discussion in their free time and have usually other jobs to do. Thanks for visualizing your...21 replies | 4167 view(s)
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13th October 2019, 06:45A wire between the differential output nodes is usually understood as short. Review the post #1 schematic.9 replies | 536 view(s)
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13th October 2019, 06:31Read about metal cladded PCB.1 replies | 167 view(s)
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12th October 2019, 21:00FvM replied to a thread Protecting the inputs of HV7802 current monitor from damage due to inrush current in Analog Circuit DesignWhy? It's not suggested in the datasheet and doesn't seem to make sense. Ra is the gain setting resistor, and typically much smaller than the...4 replies | 232 view(s)
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12th October 2019, 20:07FvM replied to a thread Rigid flex Cross section OrCAD PCB Designer in PCB Routing Schematic Layout software and SimulationI have designed several combined flex/rigid PCB, but your stack up drawing doesn't yet make sense to me. Usually the layers of the flex part...2 replies | 286 view(s)
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11th October 2019, 10:37What's the resistor tolerance?8 replies | 337 view(s)
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11th October 2019, 09:42FvM replied to a thread Voltage to frequency conversion using VFC32 in Elementary Electronic Questions50 pF doesn't fit your formula. It get > 200 pF. Did you check the integrator and pulse output waveforms? How do you measure frequency?7 replies | 359 view(s)
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11th October 2019, 09:02A few mV is well in the range of expectable MCP6002 offset voltage. When you say the error changes with input voltage, how do you measure it? DC or...8 replies | 337 view(s)
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11th October 2019, 07:43Instead of lengthy explanations, can you simply sketch which form of eddy currents you expect? I presume you agree that there must be eddy...21 replies | 4167 view(s)
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10th October 2019, 22:32If you read the datasheet of the used opto coupler, you realize that the shown recovery delay is in the expectable range. The fast attack time is in...11 replies | 503 view(s)
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10th October 2019, 13:06FvM replied to a thread Simple question on Transresistance Amplifier circuit in Analog Circuit DesignThe typical case where you apply bias is for increasing the photo diode speed (reduced junction capacitance with reverse bias voltage). Linearity...5 replies | 273 view(s)
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10th October 2019, 12:40FvM replied to a thread Microstrip line and ground on same layer in RF, Microwave, Antennas and OpticsSaturn PCB is exclusive by calculating an increased impedance with additional coplanar ground. Other professional tools like Polar Instruments Si6000...14 replies | 638 view(s)
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10th October 2019, 12:13It's not possible without an analog function. Verilog is only describing digital signals. I have seen the FPGA development boards that implemented...8 replies | 560 view(s)
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10th October 2019, 09:19FvM replied to a thread What is the vhdl equivalent of "initial begin" to initialize a ROM. in PLD, SPLD, GAL, CPLD, FPGA DesignThe code only defines the ROM content. It's translated to a *.hex file by the FPGA synthesis tool and linked to the bit file. Hardware to load the...14 replies | 556 view(s)
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9th October 2019, 22:27FvM replied to a thread Instrumentation AMP Virtual short. in Hobby Circuits and Small Projects ProblemsAgree with your explanation. But it doesn't apply to instrumentation amplifier like AD8421. It has no external feedback.5 replies | 653 view(s)
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9th October 2019, 22:17No useful SPI timing generated. Using timer interrupt to trigger the conversion is o.k., but the relation of CS and SPI_Receive isn't right. ...27 replies | 1184 view(s)
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9th October 2019, 22:10FvM replied to a thread Instrumentation AMP Virtual short. in Hobby Circuits and Small Projects ProblemsNo, instrumentation amplifier works different than basic OP. No "virtual short" involved. The sketched schematic has no relation to instrumentation...5 replies | 653 view(s)
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9th October 2019, 21:56FvM replied to a thread What is the vhdl equivalent of "initial begin" to initialize a ROM. in PLD, SPLD, GAL, CPLD, FPGA DesignIt's surely possible to design a RAM that is loaded by the FPGA fabric at run time. However the ROM initialisation examples discussed in this thread...14 replies | 556 view(s)
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9th October 2019, 18:22FvM replied to a thread What is the vhdl equivalent of "initial begin" to initialize a ROM. in PLD, SPLD, GAL, CPLD, FPGA DesignThere are many possible reasons why you may want to describe the ROM content in HDL, e.g. use the language features to calculate a lookup table as in...14 replies | 556 view(s)
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9th October 2019, 16:14Notebook and monitor are likely having low voltage DC power supply, e.g. 15 to 19V. They can be better supplied with a small boost DC converter (in...6 replies | 291 view(s)
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