FvM
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Yesterday, 14:11Considering that the questions show rather shallow RF knowledge, it should be at least mentioned that the dipole frequency range is small and...16 replies | 365 view(s) -
Yesterday, 13:30Actually not at any frequency. 75 ohm at the frequency where the dipole length equals λ/2.16 replies | 365 view(s)
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Yesterday, 12:34Obviously, the question can't be answered without considering the intended system purpose, data paths and processing. You are presuming a FPGA,...3 replies | 205 view(s)
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Yesterday, 12:25FvM replied to a thread Rise times and fall times of fast transistors seem way too long in Elementary Electronic QuestionsApart from the difference between saturated switching and small signal amplifier operation, do you understand the meaning of fT? It's the frequency...3 replies | 185 view(s)
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Yesterday, 12:12You rarely achieve exact impedance matching and it's not strictly required for a receiver. Just lose a bit of sensitivity. Different antenna types...16 replies | 365 view(s)
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Yesterday, 12:03Not sure if the piezo sensor pick up the fundamental frequency (1 - 10 Hz) acceleration or the click impact sound (kHz range). Lower and upper...6 replies | 181 view(s)
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Yesterday, 11:36FvM replied to a thread Inductance of coile dup cbale on winch (twisted pair or just two strand) in Power ElectronicsInductance of a balanced line depends on conductor geometry. Twist has no considerable effect, except for slightly increasing the effective length. ...2 replies | 144 view(s)
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21st February 2020, 17:42An antenna with 50 ohms impedance is behaving like a 50 ohms resistor in the operation frequency range of the antenna. An ideal antenna has no...16 replies | 365 view(s)
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21st February 2020, 16:40FvM replied to a thread How to get the operating temperature ( case temperature) in Thermal ManagementIn still air, the center case top temperature of the package can be expected to be not much below the chip temperature, e.g. 10 - 20 K. We usually...3 replies | 118 view(s)
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21st February 2020, 16:33Executable binary is part of the *.elf content. It can be extracted with tools for the respective processor. More easily, you can instruct the IDE...2 replies | 155 view(s)
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20th February 2020, 17:49You can use epoxy glue. I presume, it's a plastic package without dedicated thermal interface. Don't expect strong cooling effect by the heat sink....4 replies | 165 view(s)
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20th February 2020, 17:36FvM replied to a thread Why some PCB has copper circles on top and bottom layer? in PCB Routing Schematic Layout software and SimulationThese patterns are for so called "copper balancing" purposes, to achieve more uniform etching and additive copper deposition during PCB...1 replies | 168 view(s)
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20th February 2020, 11:48dpaul replied to a thread [SOLVED] Values of set/ reset when Instantiating ODDR? in PLD, SPLD, GAL, CPLD, FPGA DesignYou set the "SRTYPE" to either "SYNC" or "ASYNC" depending on the reset signal used in your design. E.g. - If you have a sync reset, then the ODDR...3 replies | 238 view(s) -
20th February 2020, 09:10dpaul replied to a thread [SOLVED] Values of set/ reset when Instantiating ODDR? in PLD, SPLD, GAL, CPLD, FPGA DesignTake a look at the ODDR for 7 series library guide....3 replies | 238 view(s)
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20th February 2020, 08:23FvM replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA DesignSee how 2 MHz clock is derived from DDS MSB phase. You can generate 4 MHz in a similar way by utilizing phase too.15 replies | 857 view(s)
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19th February 2020, 23:20Look again, the circuit is fine. If you don't have one of those "digital transistors" with built-in base resistors, you need to add an external...3 replies | 206 view(s)
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19th February 2020, 22:53FvM replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA DesignThe xapp868 design is a digital PLL that can easily generate 4 MHz along with the 2 MHz output.15 replies | 857 view(s)
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19th February 2020, 22:40FvM replied to a thread Phase detector with synchronous logic (FPGA) in RF, Microwave, Antennas and OpticsI don't agree. You get a much higher phase resolution by I/Q demodulation, only limited by the ADC resolution and signal noise.13 replies | 602 view(s)
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19th February 2020, 08:38The filter has still a fair attenuation at the 700 kHz fundamental. If you want stronger high frequency filter effect, you can go for other...8 replies | 284 view(s)
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18th February 2020, 17:47FvM replied to a thread Phase detector with synchronous logic (FPGA) in RF, Microwave, Antennas and OpticsI agree that processor is simpler. Additional logic (e.g. FPGA) is however needed due to the high sample rate, unless you have a fast signal...13 replies | 602 view(s)
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18th February 2020, 17:12FvM replied to a thread Phase detector with synchronous logic (FPGA) in RF, Microwave, Antennas and OpticsA possible solution could be to determine the analysis frequency based on the zero crossings and then multiply the acquired signal with sine and...13 replies | 602 view(s)
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18th February 2020, 09:18U2 LED reversed, but I see what you mean. You should know. If circuit isolation is a safety feature, your present design may also conflict with...24 replies | 921 view(s)
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18th February 2020, 08:34FvM replied to a thread Phase detector with synchronous logic (FPGA) in RF, Microwave, Antennas and OpticsThe 50 us limitation wasn't mentioned yet. In this case, "processing the entire dataset" is in fact more promising. Question is if you know the exact...13 replies | 602 view(s)
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17th February 2020, 23:11FvM replied to a thread 14 bit adc output to 5 bit data conversion in VHDL in PLD, SPLD, GAL, CPLD, FPGA DesignMay be the question is that trivial, may be some specific coding is intended. The OP missed to ask a clear question.3 replies | 349 view(s)
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17th February 2020, 23:03FvM replied to a thread Phase detector with synchronous logic (FPGA) in RF, Microwave, Antennas and OpticsThe multiply idea sketched in post #1 is basically good, but it should be extended to I/Q demodulation to work over 0 to 360 degree. You can either...13 replies | 602 view(s)
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17th February 2020, 13:51dpaul replied to a thread ISCAS 89-s38417 testbench required in ASIC Design Methodologies and Tools (Digital)I see the 'bench' files here http://www.pld.ttu.ee/~maksim/benchmarks/iscas89/bench/ also the core number you have listed. Was a simple google...2 replies | 292 view(s)
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17th February 2020, 13:05May be mathematically correct, but wrong in Z transform context.4 replies | 279 view(s)
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17th February 2020, 10:05Don't think so. U1 LED is driven with wrong polarity and has negative transistor supply. Many previously mentioned problems are still present,...24 replies | 921 view(s)
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17th February 2020, 09:33FvM replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA DesignA bit more complex. You'll design a kind of software PLL with 2 and 4 MHz output, locked to the 2 MHz reference. Dynamic phase shift might be used if...15 replies | 857 view(s)
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17th February 2020, 09:21High Voltage Coupling means what, exactly? Measuring current, voltage, linearly, which range? HCPL-0370 reference suggest you want to compare current...2 replies | 178 view(s)
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