FvM
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Today, 10:18dpaul replied to a thread Is it necessary to set FPGA and ASIC operating frequency to the same amount? in ASIC Design Methodologies and Tools (Digital)I would say first do the analysis for ASIC impl. You will get a max clk value, above which you will have clock violations. Keep that fixed for ASIC....5 replies | 149 view(s) -
Today, 09:42FvM replied to a thread Recomended grounding methods of Analog ground and ground plane in Elementary Electronic QuestionsYour schematic has wrongly connected the exposed pad to PGND, should be AGND. The connection between AGND and PGND is usually made by PCB copper...2 replies | 44 view(s) -
Yesterday, 17:08FvM replied to a thread NFC Antenna Design to radiate strong field strength in RF, Microwave, Antennas and OpticsThe field strength of a circular coil can be easily calculated using Biot-Savart's law. See...2 replies | 166 view(s)
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Yesterday, 00:06The code should work, but measuring peak-to-peak current magnitude is sensitive to waveform distortions and noise and in so far the least accurate...22 replies | 426 view(s)
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20th November 2019, 17:40ADE7878 is not recommended for new designs, ADE7878A ist the recent type. I agree with KlausST. You need a poly phase energy meter IC to support...8 replies | 277 view(s)
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20th November 2019, 17:21If isolation required, LLC converter, otherwise multiphase synchronous boost.5 replies | 176 view(s)
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20th November 2019, 13:31FvM replied to a thread Resonant Converter Simulation Problem in Hobby Circuits and Small Projects ProblemsMake the total load impedance inductive to achieve zero voltage switching and reduce switching losses. General consideration about LLC operation...6 replies | 240 view(s)
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20th November 2019, 13:28FvM replied to a thread How to Measure Creepage Distance in PCB Routing Schematic Layout software and Simulationpin-to-pin seems pretty easy, use a ruler or measure in 3D-model Find some consideration about heatsink creepage in Infineon AN2012-10...5 replies | 166 view(s)
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20th November 2019, 12:58FvM replied to a thread How to Measure Creepage Distance in PCB Routing Schematic Layout software and SimulationThere are several creepage paths involved with TO220, e.g. pin-to-pin, at the case and at the PCB, heatsink to tab, etc. Can you ask more specific?5 replies | 166 view(s)
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20th November 2019, 12:52FvM replied to a thread Resonant Converter Simulation Problem in Hobby Circuits and Small Projects ProblemsI think you are mixing several topics. - An induction heater may use a parallel capacitor to compensate the low coil inductance (air coil or coil...6 replies | 240 view(s)
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20th November 2019, 12:30Not when represented with long data type as in post #12.16 replies | 701 view(s)
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20th November 2019, 12:23FvM replied to a thread Design a system clock monitor in verilog in PLD, SPLD, GAL, CPLD, FPGA DesignYes, using an auxiliary clock, e.g. built-in FPGA RC oscillator. Usually a clock monitor makes only sense if you have second clock you can switch...3 replies | 217 view(s)
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20th November 2019, 09:32b=65535 is outside Q1.15 (int16) range. Should be -1.16 replies | 701 view(s)
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20th November 2019, 09:28FvM replied to a thread Resonant Converter Simulation Problem in Hobby Circuits and Small Projects ProblemsHow do you determine resonant frequency? Resonant converter can be hard switching series resonant LC converter or better soft switching LLC...6 replies | 240 view(s)
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20th November 2019, 09:22Apparently you don't scale the multiply result correctly.16 replies | 701 view(s)
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20th November 2019, 00:22FvM replied to a thread Switch +/- 15v supply for audio preamp in Hobby Circuits and Small Projects ProblemsDo you need isolation between SPI and supply switches? If not, there are simpler solutions than optoMOS.6 replies | 326 view(s)
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20th November 2019, 00:05FvM replied to a thread $freq while using AC analysis to access lookup table in Analog Circuit DesignForgot to mention the circuit analysis tool.10 replies | 396 view(s)
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20th November 2019, 00:00The circuit is rather unclear because you are showing less than half of the DC/DC pins. Each converter has two input and three output pins.4 replies | 232 view(s)
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19th November 2019, 19:45See below an example of plotting transistor capacitances over Vds in Ltspice.7 replies | 276 view(s)
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19th November 2019, 13:25Im under the impression, you are trying to drag on the thread without ever looking into the 18F2550 datasheet… Simply notice that the PLL has...4 replies | 266 view(s)
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19th November 2019, 13:18Please some more snippets of specification. Waveform, rise-/falltime, pulse width, magnitude, just to mention a few parameters.7 replies | 304 view(s)
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19th November 2019, 13:13FvM replied to a thread Multiple pulse width ( 5 pulses ) inverter and lowest low order harmonics in Mathematics and PhysicsYes, exactly.17 replies | 670 view(s)
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19th November 2019, 10:18RF should be ok then.12 replies | 610 view(s)
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19th November 2019, 10:13FvM replied to a thread Difference circuit not acting as expected in Analog Integrated Circuit (IC) Design, Layout and FabricationLooks like single supply OP in saturation.3 replies | 172 view(s)
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19th November 2019, 09:25FvM replied to a thread Multiple pulse width ( 5 pulses ) inverter and lowest low order harmonics in Mathematics and PhysicsSorry for lack of clarity. r1,f1 etc. are the edge times (rising 1, falling 1,...) in rad. To get the full picture, you should review the original...17 replies | 670 view(s)
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18th November 2019, 23:58FvM replied to a thread Multiple pulse width ( 5 pulses ) inverter and lowest low order harmonics in Mathematics and PhysicsThe emphasis of the presented results is on the feasibility of harmonic cancellation over a certain magnitude range. I'm assuming that this solution,...17 replies | 670 view(s)
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18th November 2019, 19:13Crystal oscillator output has DC bias of Vcc/2, RF in bias is unknown. Where is it connected to? Use capacitor to clock oscillator DC bias. It's...12 replies | 610 view(s)
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18th November 2019, 17:26For correct double balanced mixer operation (e.g. achieving the specified LO to IF isolation), RF and LO inputs must be DC free. According to your...12 replies | 610 view(s)
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18th November 2019, 16:24dpaul replied to a thread Using a BFM in system verification code. in ASIC Design Methodologies and Tools (Digital)Did you consult the *_user_manual.pdf that comes with the download? You have written the master module, so you need to use the BFM as a slave. ...6 replies | 347 view(s)
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18th November 2019, 15:56Can't comment unknown measurements.16 replies | 450 view(s)
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