FvM
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Today, 00:33FvM replied to a thread Adding a 3 band equalizer to a phantom powered electret mic amp in Analog Circuit DesignIt's rarely the microphone that's responsible for "ring at certain frequencies" and it's quite unusual to use an equalizer in front of the mixing...5 replies | 102 view(s) -
Today, 00:22You are asking about off-line SMPS, which are comprised of a rectifier, a filter capacitor and a flyback converter. Unless you are designing a PFC...2 replies | 91 view(s)
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Yesterday, 13:00FvM replied to a thread Calculating capacitor ripple current in output filter of DCDC module? in Power ElectronicsNo, no. You can review typical tan d and ESR characteristic from several manufacturers, e.g. Epcos/TDK. Tan d is roughly proportional to frequency. ...11 replies | 291 view(s)
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Yesterday, 12:07dpaul replied to a thread Changing the ModelSim version that comes with Libero SoC v12.3 in PLD, SPLD, GAL, CPLD, FPGA DesignWell I did ask for that and the local FAE told me that it won't be provided. They will provide the compiled libraries for the 64bit DE version. ...14 replies | 1186 view(s) -
Yesterday, 11:40FvM replied to a thread Impedance vs frequency plot of input filter of SMPS? in Analog Circuit DesignSurprising that the datasheet shows several filter circuits with impedance curve, but none is specifying the inductor series resistance. Basic...2 replies | 155 view(s)
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Yesterday, 11:28FvM replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA DesignI was referring to xapp868 where a 32 bit DDS is running at 2.048 MHz. Not sure how your design is different. What's the DDS phase accumulator...18 replies | 1022 view(s)
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Yesterday, 11:18FvM replied to a thread Need to ensure SMPS output filter has at least 10mR of ESR...use "ESR resistor"? in Power ElectronicsThat's not how you calculate it. Loss factor is specified for 100 Hz. ESR is decreasing between 100 Hz and 10 kHz, but not more than several 10...7 replies | 208 view(s)
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Yesterday, 09:41FvM replied to a thread Need to ensure SMPS output filter has at least 10mR of ESR...use "ESR resistor"? in Power ElectronicsPartially, yes. You need to calculate the total ESR of the C-RC combination at 11 kHz. A slightly higher resistance value, e.g. 20 mohms could be...7 replies | 208 view(s)
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Yesterday, 09:29Any reference for this statement (product data sheet, literature quote)? I would expect inductive sensor loop as mentioned in post #2 and #9.13 replies | 4997 view(s)
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23rd February 2020, 23:25L_stage1 hardly. Bias2 may be, depending on the intended quiescent current. What's against class A?7 replies | 342 view(s)
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23rd February 2020, 18:21A software defined radio USB stick like nooelec NESDR covers the 25MHz - 1750MHz frequency range for about $25.13 replies | 492 view(s)
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22nd February 2020, 14:11Considering that the questions show rather shallow RF knowledge, it should be at least mentioned that the dipole frequency range is small and...16 replies | 530 view(s)
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22nd February 2020, 13:30Actually not at any frequency. 75 ohm at the frequency where the dipole length equals λ/2.16 replies | 530 view(s)
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22nd February 2020, 12:34Obviously, the question can't be answered without considering the intended system purpose, data paths and processing. You are presuming a FPGA,...3 replies | 249 view(s)
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22nd February 2020, 12:25FvM replied to a thread Rise times and fall times of fast transistors seem way too long in Elementary Electronic QuestionsApart from the difference between saturated switching and small signal amplifier operation, do you understand the meaning of fT? It's the frequency...3 replies | 320 view(s)
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22nd February 2020, 12:12You rarely achieve exact impedance matching and it's not strictly required for a receiver. Just lose a bit of sensitivity. Different antenna types...16 replies | 530 view(s)
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22nd February 2020, 12:03Not sure if the piezo sensor pick up the fundamental frequency (1 - 10 Hz) acceleration or the click impact sound (kHz range). Lower and upper...6 replies | 233 view(s)
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22nd February 2020, 11:36FvM replied to a thread Inductance of coile dup cbale on winch (twisted pair or just two strand) in Power ElectronicsInductance of a balanced line depends on conductor geometry. Twist has no considerable effect, except for slightly increasing the effective length. ...2 replies | 204 view(s)
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21st February 2020, 17:42An antenna with 50 ohms impedance is behaving like a 50 ohms resistor in the operation frequency range of the antenna. An ideal antenna has no...16 replies | 530 view(s)
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21st February 2020, 16:40FvM replied to a thread How to get the operating temperature ( case temperature) in Thermal ManagementIn still air, the center case top temperature of the package can be expected to be not much below the chip temperature, e.g. 10 - 20 K. We usually...3 replies | 216 view(s)
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21st February 2020, 16:33Executable binary is part of the *.elf content. It can be extracted with tools for the respective processor. More easily, you can instruct the IDE...2 replies | 195 view(s)
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20th February 2020, 17:49You can use epoxy glue. I presume, it's a plastic package without dedicated thermal interface. Don't expect strong cooling effect by the heat sink....4 replies | 202 view(s)
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20th February 2020, 17:36FvM replied to a thread Why some PCB has copper circles on top and bottom layer? in PCB Routing Schematic Layout software and SimulationThese patterns are for so called "copper balancing" purposes, to achieve more uniform etching and additive copper deposition during PCB...1 replies | 248 view(s)
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20th February 2020, 11:48dpaul replied to a thread [SOLVED] Values of set/ reset when Instantiating ODDR? in PLD, SPLD, GAL, CPLD, FPGA DesignYou set the "SRTYPE" to either "SYNC" or "ASYNC" depending on the reset signal used in your design. E.g. - If you have a sync reset, then the ODDR...3 replies | 284 view(s)
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20th February 2020, 09:10dpaul replied to a thread [SOLVED] Values of set/ reset when Instantiating ODDR? in PLD, SPLD, GAL, CPLD, FPGA DesignTake a look at the ODDR for 7 series library guide....3 replies | 284 view(s)
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20th February 2020, 08:23FvM replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA DesignSee how 2 MHz clock is derived from DDS MSB phase. You can generate 4 MHz in a similar way by utilizing phase too.18 replies | 1022 view(s)
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19th February 2020, 23:20Look again, the circuit is fine. If you don't have one of those "digital transistors" with built-in base resistors, you need to add an external...3 replies | 238 view(s)
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19th February 2020, 22:53FvM replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA DesignThe xapp868 design is a digital PLL that can easily generate 4 MHz along with the 2 MHz output.18 replies | 1022 view(s)
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19th February 2020, 22:40FvM replied to a thread Phase detector with synchronous logic (FPGA) in RF, Microwave, Antennas and OpticsI don't agree. You get a much higher phase resolution by I/Q demodulation, only limited by the ADC resolution and signal noise.13 replies | 690 view(s)
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19th February 2020, 08:38The filter has still a fair attenuation at the 700 kHz fundamental. If you want stronger high frequency filter effect, you can go for other...8 replies | 351 view(s)
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