FvM
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Today, 22:14There's no error, just a warning.1 replies | 0 view(s) -
Today, 15:25Yes, for a first order (single pole) transfer function. The closed loop transfer function in post #1 isn't first order because it doesn't show -3 dB...6 replies | 173 view(s)
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Today, 12:59FvM replied to a thread adhesive to join PCB in PCB Routing Schematic Layout software and SimulationI don't understand the low dielectric constant point. If you join PCBs, the dielectric would be formed by the PCB substrates, a thin adhesive layer...2 replies | 82 view(s)
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Today, 12:52How's the drive displayed in Windows disk management tool? It may contain no or an incompatible file system. Disk management tool can delete the...2 replies | 71 view(s)
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Today, 09:42FvM replied to a thread How to implement a transfer function with discrete components in Analog Circuit DesignAs long you are doing an exercise without actual requirements, absolute component values don't really matter. I started with feasible capacitor...24 replies | 721 view(s)
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Today, 09:32FvM replied to a thread Cascading amplifier with a line driver for an analog signal transmission in Analog Circuit DesignThe problem has been extensively discussed in your previous thread...2 replies | 128 view(s)
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Yesterday, 22:35-1 respectively inverting amplifier5 replies | 192 view(s)
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Yesterday, 22:30FvM replied to a thread [SOLVED] Polar To Rectangular on the calculator, error in Mathematics and PhysicsDid you try with positive radius value?4 replies | 52 view(s)
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Yesterday, 15:03FvM replied to a thread Add model in Simetrix in PCB Routing Schematic Layout software and SimulationSub files are encrypted sub circuit files which can be only used with Ltspice. No support for other SPICE simulators unfortunately.2 replies | 89 view(s)
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Yesterday, 14:38From an RTL point of view... Are you registering this GPIO input properly at the clock rising edge. Sometimes multiple register stages might be...3 replies | 142 view(s) -
Yesterday, 12:11FvM replied to a thread rtl code to find the smallest in ASIC Design Methodologies and Tools (Digital)Might be fast enough for 8 bit data without pipeline.10 replies | 259 view(s)
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Yesterday, 09:491. What's the 1 pf capacitor in parallel to the input voltage source good for? 2. THS3202 is a current feedback OP, the open loop gain can be...6 replies | 173 view(s)
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Yesterday, 09:33FvM replied to a thread VHDL code flow in ISE Design Suite 14.7 in PLD, SPLD, GAL, CPLD, FPGA DesignAre you sure that the supplied servo signal is regular (not rapidly varying pulse width)? Otherwise, follow the manufacturer data sheet. Current...6 replies | 157 view(s)
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20th February 2019, 11:47Your variables are apparently 8 bit unsigned. Use 16 bit data type. I would use sprintf() for decimal output formatting. - - - Updated - - - ...5 replies | 119 view(s)
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20th February 2019, 08:56FvM replied to a thread rtl code to find the smallest in ASIC Design Methodologies and Tools (Digital)I don't see four inputs, do you mean input in; Are you looking for combinational or registered (clocked) logic? In both cases, why don't you...10 replies | 259 view(s)
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19th February 2019, 22:17The diagram title suggests so, but it makes no sense and I guess it's just a typo. At least the interpretation contradicts the max. forward volts...5 replies | 132 view(s)
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19th February 2019, 18:07The counter design is likely to cause irregular behavior by using asynchronous reset. Now, as you have moved everything to a single clock domain, all...18 replies | 385 view(s)
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19th February 2019, 17:02FvM replied to a thread How to implement a transfer function with discrete components in Analog Circuit DesignO.K., just an exercise. As you see, it can be implemented. There are however additional problems related to input signal level and OP voltage...24 replies | 721 view(s)
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19th February 2019, 16:51FvM replied to a thread [SOLVED] Help to translate verilog code lines to vhdl in PLD, SPLD, GAL, CPLD, FPGA DesignYes you created a new topic, but according forum rules it's not appropriate, they say That's clearly a related question, without the original...9 replies | 186 view(s)
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19th February 2019, 15:39FvM replied to a thread Embedded project needs devices which can work continuously at +125 degree C in MicrocontrollersThat's how SPI bus works. Review the interface description in datasheet, SO has internal tri-state driver enabled by CS.79 replies | 2066 view(s)
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19th February 2019, 15:33FvM replied to a thread [SOLVED] Help to translate verilog code lines to vhdl in PLD, SPLD, GAL, CPLD, FPGA DesignThe definition of wbus_count doesn't make sense, it must be two-dimensional to make the assignment work. Presently RHS is std_logic and LHS 10 bit...9 replies | 186 view(s)
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19th February 2019, 15:14The estimation is valid for first order low-pass respectively system with dominant pole. To keep 500 ps rise time of a band limited input signal, the...10 replies | 218 view(s)
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19th February 2019, 14:57More or less. There's no typical Vf specification in the datasheet, only maximal. Seeing actually about 1V Vf at 0.1A is a bit surprising, but yes,...5 replies | 132 view(s)
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19th February 2019, 14:47Some can be probably used. The specification is however incomplete: - DC capable amplifier yes/no - gain respectively output level -...10 replies | 218 view(s)
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19th February 2019, 12:51With only 150 Hz bandwidth, there's absolutely no advantage in using fully differential signaling between amplifier and DAQ board. Instead you can...5 replies | 192 view(s)
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19th February 2019, 12:41FvM replied to a thread Where to find Altera PLDShell v5.0 Software in PLD, SPLD, GAL, CPLD, FPGA DesignI rather thought, support has ended at least 10 years ago... As far as I'm aware of, EP300 series is compatible to industry standard PAL/GAL...4 replies | 171 view(s)
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19th February 2019, 12:11You are describing the problem with inappropriate terminology. You are not "adding frequencies", you are combining signals. Combining signals...3 replies | 257 view(s)
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19th February 2019, 10:01Single phase synchronous motors usually have low starting torque. It might be that the motor isn't suited for your application. Motors with run...3 replies | 134 view(s)
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19th February 2019, 09:37The most simple solution is to use synchronizer logic that generates a clock enable pulse in the 40 MHz domain for each rising edge of rf_in and...18 replies | 385 view(s)
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19th February 2019, 09:20FvM replied to a thread VHDL code flow in ISE Design Suite 14.7 in PLD, SPLD, GAL, CPLD, FPGA DesignReviewing your code can help. Look at the integer range definition of divrel1. Range of 0 to 1500 is implemented as 11 bit unsigned in synthesis,...6 replies | 157 view(s)
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