FvM
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Yesterday, 12:23The maximum PWM frequency is actually fclk/(4*4096), there's an additional prescaler.6 replies | 170 view(s) -
Yesterday, 07:49I see that medium power transistors like FMMT495, MMBT5550 or BCX41 have apparently sufficient thermal capacity to handle the requested pulse load,...6 replies | 193 view(s)
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Yesterday, 07:08FvM replied to a thread Sampling Bandwidth vs. Bandwidth in Tracking Mode of a Sample/Track and Hold in Analog Circuit DesignI doubt that both terms have clearly commonly understood definitions. The original post is apparently referring to a paper or datasheet. If so, why...5 replies | 445 view(s)
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6th April 2020, 21:4610 ms is much too long for the small thermal capacitance of low power SOT23 transistor, e.g. BC847. A medium power transistor in SOT23 with larger...6 replies | 193 view(s)
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6th April 2020, 18:24FvM replied to a thread Differential pair with dynamic resistance in Elementary Electronic QuestionsT2 is not saturated with Rc=2k, only with 20k.3 replies | 126 view(s)
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5th April 2020, 10:21FvM replied to a thread Waht is the name of ATX connector on motherboard? in Hobby Circuits and Small Projects ProblemsMolex Mini-Fit Jr series2 replies | 246 view(s)
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5th April 2020, 09:46FvM replied to a thread How to trace the original of netlist gates back to the original RTL description in ASIC Design Methodologies and Tools (Digital)Did you try to synthesize with different optimizer goals and timing constraints? A possible reason for increased power consumption could be that the...6 replies | 442 view(s)
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5th April 2020, 09:41FvM replied to a thread Please help me avoid a disaster with my first pcb in Hobby Circuits and Small Projects ProblemsProcessed copper thickness is the relevant parameter for trace resistance and current rating. Outer layer copper is build by electrolytic deposition...9 replies | 482 view(s)
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4th April 2020, 23:03If I understand right, you are trying to build a saturable reactor. The type shown in the first link can't be build on a single core. Sending current...6 replies | 394 view(s)
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4th April 2020, 13:43FvM replied to a thread Please help me avoid a disaster with my first pcb in Hobby Circuits and Small Projects ProblemsVCCIO is the 5V output of DCDC, I think it's o.k. to route it this way.9 replies | 482 view(s)
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4th April 2020, 13:26I would immediately move the thread to ASIC section - if it had any ASIC related questions. But yet there are none. Please review your questions.9 replies | 770 view(s)
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4th April 2020, 12:18I don't see a relation of your previous questions to ASIC design, it's neither mentioned nor obvious in any regard. The discussed problems, although...9 replies | 770 view(s)
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4th April 2020, 11:45FvM replied to a thread Please help me avoid a disaster with my first pcb in Hobby Circuits and Small Projects ProblemsNot completely clear which net is addressed. Regarding the double side population, I understand that it can be only realized with hand soldering....9 replies | 482 view(s)
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3rd April 2020, 22:46A mass storage device is operated with read and write to logical blocks, the file management is performed by the controlling computer. Interrupting a...9 replies | 770 view(s)
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3rd April 2020, 22:19FvM replied to a thread Solving issues in my PCB grounding in Professional Hardware and Electronics DesignThe SMPS is a Class I device, designed to be operated with proper proctective earth connection. The problem description suggests that the PE...6 replies | 327 view(s)
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3rd April 2020, 22:06FvM replied to a thread Generating a digital pulse of 10 secs and 1 sec in PLD, SPLD, GAL, CPLD, FPGA DesignHow about building a digital timer? Can be made in programmable logic, but also using a microcontroller or by assembling discrete logic ICs. All...2 replies | 203 view(s)
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2nd April 2020, 23:20FvM replied to a thread Def-Stan 59-411 proble with MOVs don't dissipate energy in RF, Microwave, Antennas and OpticsI wonder if the used MOV are actually rated for the applied DCS12 test signals, which are considerably different from industry standard surge test...2 replies | 230 view(s)
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2nd April 2020, 23:02No idea where you got the integral expression. I guess " ∫ t 0" is a garbled form of "integral from 0 to t", which would be the correct description...4 replies | 491 view(s)
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2nd April 2020, 22:01FvM replied to a thread water flow detection in a pipe in Hobby Circuits and Small Projects ProblemsConsider flow and pressure as independent parameters. Pressure is important for "invasive" sensors. 0,015 m/s seems correct and is quite low. An...6 replies | 518 view(s)
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2nd April 2020, 12:41dpaul replied to a thread My test pattern is not like should be! Somebody can help me please? in PLD, SPLD, GAL, CPLD, FPGA DesignHello OP, As I deduce that you are looking to learn about video frame buffers, see here.......9 replies | 613 view(s) -
2nd April 2020, 11:47The ringing occurs in discontinuous mode when the rectifier current flow stops. It's a high impedance/low energy oscillation (frequency set by main...23 replies | 1008 view(s)
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1st April 2020, 21:50Or referring to ∫Vdt (ET in your terminologie) I = ∫Vdt/L22 replies | 935 view(s)
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1st April 2020, 16:07FvM replied to a thread Experienced CADSTAR user's in PCB Routing Schematic Layout software and SimulationYou should take a look at Pulsonix. The Software has been developed by former Racal Redac (the origin of Cadstar) guys. The look and feel is still...2 replies | 334 view(s)
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1st April 2020, 16:03FvM replied to a thread Solving issues in my PCB grounding in Professional Hardware and Electronics DesignI guess there's no high voltage generated on the board. Hence it's a problem of the power supply. What is it?6 replies | 327 view(s)
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1st April 2020, 09:31Should not be. Better you ask this in the Xilinx forums. As for your AXI enlightenment and wisdom, I would recommend reading all the AXI related...126 replies | 5819 view(s)
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31st March 2020, 11:55Non of the question can be answered without referring to the specific USB device type und functionality. Which device are asking about?9 replies | 770 view(s)
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31st March 2020, 08:42dpaul replied to a thread Conflict between two axi masters. in ASIC Design Methodologies and Tools (Digital)I cannot comment more. You need to check individual axi channel transactions and verify that the channel handshakes are happening properly. Maybe...5 replies | 382 view(s)
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31st March 2020, 08:35dpaul replied to a thread Tool for transforming python code to FPGA for Machine Learning in PLD, SPLD, GAL, CPLD, FPGA DesignDid you look into PYNQ and the libraries therein? http://www.pynq.io/18 replies | 1555 view(s)
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