FvM -

Today, 14:46

FvM replied to a thread IR2110 High Side Problem in Power Electronics

Nothing has been said about DC link voltage, SS34 (40 V schottky) can work for low voltage. But bootstrap capacitor of 100 nF works in no way for 50...

6 replies | 156 view(s)

Today, 14:38

FvM replied to a thread ltspice hierarchical circuit error in PCB Routing Schematic Layout software and Simulation

I don't understand what your problem is. You can instantiate the symbol and connect it. Apparently a correct net list is generated. The best way...

4 replies | 126 view(s)

Today, 14:17

FvM replied to a thread adjustable voltage and current power supply in Power Electronics

In relation to the intended function (adjustable constant I/V power supply with switch mode pre-regulator), the circuit isn't overly complex at first...

8 replies | 212 view(s)

Today, 12:02

FvM replied to a thread Noise in CMOS Inverter in Analog Circuit Design

Which simulation circuit are you talking about? The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback...

26 replies | 978 view(s)

Today, 11:34

FvM replied to a thread Noise in CMOS Inverter in Analog Circuit Design

Sounds like you have forgotten the thread questions in the meantime. The problem was to measure output impedance. You necessarily need to ground the...

26 replies | 978 view(s)

Yesterday, 08:46

FvM replied to a thread what are the risks for isolating test equipment by negating earth ground in Elementary Electronic Questions

The idea of an isolation or safety transformer is to provide a supply voltage without earth connection. Respectively they are exposing the output...

9 replies | 249 view(s)

Yesterday, 08:34

FvM replied to a thread Trying to pass and return a variable to a function returns uneffected value in Microcontrollers

The usual solution is to pass the variable by reference rather than by value. Review your C programming text book. void Filter(unsigned int...

6 replies | 394 view(s)

15th June 2018, 12:27

FvM replied to a thread what are the risks for isolating test equipment by negating earth ground in Elementary Electronic Questions

Test equipment, e.g. an oscilloscope, is usually designed to be operated with PE connection. Leakage currents and insulation parameters are not...

9 replies | 249 view(s)

15th June 2018, 10:37

FvM replied to a thread Transmit data by Connect two ADSL modems over copper telephone line up to 1KM in Digital communication

No. By definition of term, DSL uses telephone lines. I just noticed, that some products are advertized, didn't check about prices and availability. ...

15 replies | 549 view(s)

15th June 2018, 06:20

FvM replied to a thread digital pot rather than analog pot in Analog Circuit Design

Connect P0A to a virtual ground node, a sufficient large capacitor to ground (e.g. 1 µF) and a voltage divider generating Vdd/2. It's not obvious...

7 replies | 165 view(s)

15th June 2018, 06:07

FvM replied to a thread Loop-gain calculation in Analog Circuit Design

As already mentioned, the circuit can be used in a way that doesn't establish feedback across the outer terminals. If the amplifier cell is an OP IC...

26 replies | 594 view(s)

14th June 2018, 23:03

FvM replied to a thread Loop-gain calculation in Analog Circuit Design

Apparently the professor did a bad job in conveying the purpose of the analysis. But I absolutely disagree about "inefficient and outdated"....

26 replies | 594 view(s)

14th June 2018, 15:58

FvM replied to a thread Phase peering RF cable assemblies in RF, Microwave, Antennas and Optics

I don't recognize a commonly understood technical term. You should tell where do you see the term, e.g. a quote with context.

2 replies | 176 view(s)

14th June 2018, 15:47

FvM replied to a thread Loop-gain calculation in Analog Circuit Design

Why particularly the "actual" input? A loop is created by feeding back a signal from amplifier output to input. In the given circuit, the drain node...

26 replies | 594 view(s)

14th June 2018, 15:40

FvM replied to a thread Verilog code for BCD to Floating point representation in PLD, SPLD, GAL, CPLD, FPGA Design

A bit of guessing, yes. Post #3 however suggests scaling to 3.3V, post #11 4 digits.

18 replies | 365 view(s)

14th June 2018, 09:36

FvM replied to a thread digital pot rather than analog pot in Analog Circuit Design

Not sure what you mean with "tiny sound fluctuations"? An effectively useless description. You missed however to tell the used digipot type and...

7 replies | 165 view(s)

14th June 2018, 09:06

FvM replied to a thread Transmit data by Connect two ADSL modems over copper telephone line up to 1KM in Digital communication

Google for "DSL modem leased line" and review available commercial products.

15 replies | 549 view(s)

14th June 2018, 09:01

FvM replied to a thread How to calculate log10(n) in Verilog in PLD, SPLD, GAL, CPLD, FPGA Design

The recursive calculation scheme can't be used as hardware logic description, otherwise the number of recursions must be known at synthesis time. ...

12 replies | 249 view(s)

14th June 2018, 08:51

FvM replied to a thread Verilog code for BCD to Floating point representation in PLD, SPLD, GAL, CPLD, FPGA Design

Which value is converted to bcd? As mentioned before, the ADC value must be first scaled, e.g. to integer millivolt 0- 3300 and the converted to bcd....

18 replies | 365 view(s)

14th June 2018, 08:43

dpaul replied to a thread How to calculate log10(n) in Verilog in PLD, SPLD, GAL, CPLD, FPGA Design

Then you must learn Verilog first. Why would someone do the conversion for you, it is your task!

12 replies | 249 view(s)

14th June 2018, 08:37

FvM replied to a thread Loop-gain calculation in Analog Circuit Design

Consider a setup without additional external feedback, e.g. Vin connected to a voltage source. Then the internal feedback through R2 (feedback factor...

26 replies | 594 view(s)

13th June 2018, 22:40

FvM replied to a thread Flyback PFC passes mains harmonics in Power Electronics

What do you mean with "passes all mains harmonics"? There's no indication for harmonic behaviour in the posted waveform.

4 replies | 140 view(s)

13th June 2018, 15:22

dpaul replied to a thread Build an Adder using VHDL in PLD, SPLD, GAL, CPLD, FPGA Design

Any undergraduate digital design text-book teaches you how to build an adder using logic gates. Study that and then apply that concept in VHDL to...

10 replies | 252 view(s)