FvM
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Yesterday, 23:30No. I'm only talking about a way to analyze the operation mode. As said, there's no simple solution, except for reducing the controller gain.29 replies | 1869 view(s) -
Yesterday, 15:07Thanks, I didn't realize that it's a 3525 hardware pwm controller. I guess, instability occurs when the output current transits to discontinuous mode...29 replies | 1869 view(s)
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Yesterday, 13:52It looks like the gate control is paused intentionally by the controller circuit. If so, it's a software rather than power electronics problem. Any...29 replies | 1869 view(s)
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Yesterday, 12:48According to IEC 61000-3-2 Limits for harmonic current emissions (equipment input current ≤16 A per phase), professional equipment (defined as:...19 replies | 826 view(s)
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Yesterday, 12:17Seriously, before starting a PCB design, you should have at least a shallow knowledge of ZYNC document structure. Designing IO bank supply...4 replies | 283 view(s)
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Yesterday, 11:50FvM replied to a thread Voltage input to BLDC inverters on tethered drone? in Elementary Electronic QuestionsHow did you advance from 1.2 kW to 12.5 kW drone power supply? I presume there are very few civil applications for this technology.18 replies | 957 view(s)
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Yesterday, 11:35Just for clarification, you are talking about 40 mAh NiMH button cells? If so, trickle charge current of 1.1 mA seems appropriate. Standby current is...2 replies | 238 view(s)
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Yesterday, 11:09FvM replied to a thread how to find processing time of an algoritm in Vivado 2017? in PLD, SPLD, GAL, CPLD, FPGA DesignThe processing time is fixed by algorithm design and doesn't depend on Vivado software. Are you talking about a pipelined design that reads one...1 replies | 155 view(s)
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25th January 2020, 18:30If it's dimmable LED, what's the specification? Typically they use trailing edge phase control.28 replies | 591 view(s)
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25th January 2020, 14:08You can alternatively drive the 555 charge/discharge resistors by OUT pin, leaving DIS pin unconnected. Some flickering can be expected due to 500...28 replies | 591 view(s)
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25th January 2020, 12:39It doesn't actually matter in this case, but your gate drive power calculation is completely wrong. Neither gate Iavg nor Irms is significant,...28 replies | 591 view(s)
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25th January 2020, 11:49If you perform only 1 measurement per second, 40 µs division time (0.004 %) would be absolutely no issue. But I guess 1 Hz is too slow. For...7 replies | 318 view(s)
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25th January 2020, 11:19I haven't yet found a differential probe that is suitable for measuring high side gate voltage without huge common mode crosstalk. I didn't yet check...8 replies | 293 view(s)
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24th January 2020, 19:59For the said measurement application (high side gate voltage), you need really high CMRR and a probe design that doesn't send common mode currents...8 replies | 293 view(s)
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24th January 2020, 14:07dpaul replied to a thread Interface Logic Model in Synosys is obsolete in ASIC Design Methodologies and Tools (Digital)What does the command reference manual say? Have you looked there?2 replies | 323 view(s) -
24th January 2020, 14:02dpaul replied to a thread Get some advice and tips to design ETHERNET switch or even TSN switch on FPGA in PLD, SPLD, GAL, CPLD, FPGA DesignI know that and assumed the OP knows the difference. If he is a beginner in this area, it makes more sense for him to 1st understand how Ethernet...5 replies | 262 view(s)
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24th January 2020, 11:04I agree about using RS-422 or RS-485. It can work over many km in a party line topology with correct end termination. I'm however surprised that...15 replies | 588 view(s)
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24th January 2020, 10:36What's the opto triac type? I suggest an RCR filter/snubber circuit like below to prevent parasitic triggering. R2 can be reduced to 50 to 200 ohm...6 replies | 278 view(s)
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23rd January 2020, 23:59Suggest you get self-triggering of opto triac or main triac by high dv/dt. That's likely to happen with inductive load, RC filters for the opto...6 replies | 278 view(s)
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23rd January 2020, 17:17FvM replied to a thread Configuring ICE40 FPGA directly from ESP32 uC rather than using dedicated flash IC in PLD, SPLD, GAL, CPLD, FPGA Design"Slave SPI mode" in the configuration manual refers to operating the uC as SPI master and ICE40 as slave which is most likely the easier way.7 replies | 287 view(s)
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23rd January 2020, 16:07dpaul replied to a thread Get some advice and tips to design ETHERNET switch or even TSN switch on FPGA in PLD, SPLD, GAL, CPLD, FPGA DesignYou need the understand the concepts an design your own. :-)5 replies | 262 view(s)
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23rd January 2020, 12:18In my code I have a part where I am asserting a message at the Transcript window every 20us. Have added the flush() there. Works for me!3 replies | 274 view(s)
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23rd January 2020, 12:03dpaul replied to a thread Get some advice and tips to design ETHERNET switch or even TSN switch on FPGA in PLD, SPLD, GAL, CPLD, FPGA DesignIf you are using a Xilinx FPGA, I can advice you to use the TEMAC IP core (free hardware eval license) for initial understanding. Download and skim...5 replies | 262 view(s)
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23rd January 2020, 09:26You are apparently misunderstanding things. The WiFi adapters have two antenna ports for diversity purposes, each coax cable will be connected to a...1 replies | 169 view(s)
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22nd January 2020, 19:251. You can verify by checking the loop gain. 2. Choose initial conditions that result in a start magnitude below steady state. You'll see a rising...9 replies | 471 view(s)
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22nd January 2020, 16:10As explained by cariban, C1 and L1 aren't directly related, respectively there's no formula linking the values. For L1, I would use a low current...9 replies | 434 view(s)
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22nd January 2020, 15:11FvM replied to a thread Remove glitches in output frequency of ring oscillator in Elementary Electronic QuestionsWhat we see in post #1 is not jitter. It's an unstable oscillation mode. Apart from the question it's a real hardware effect or a simulation...10 replies | 502 view(s)
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22nd January 2020, 14:21Why 4.7 uF, why not 47 nF or 470 nF? You didn't yet specify any application parameters.9 replies | 434 view(s)
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22nd January 2020, 14:11FvM replied to a thread [SOLVED] LoopGain analysis with multiple feedback loop in Analog Circuit DesignSure, due to series-shunt feedback working.17 replies | 948 view(s)
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22nd January 2020, 14:09Looking at the *_simulation.log I found the following... # ** Fatal: (vsim-4) ****** Memory allocation failure. ***** # Attempting to allocate...3 replies | 274 view(s)
About FvM
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