FvM
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Yesterday, 17:47FvM replied to a thread Phase detector with synchronous logic (FPGA) in RF, Microwave, Antennas and OpticsI agree that processor is simpler. Additional logic (e.g. FPGA) is however needed due to the high sample rate, unless you have a fast signal...10 replies | 357 view(s) -
Yesterday, 17:12FvM replied to a thread Phase detector with synchronous logic (FPGA) in RF, Microwave, Antennas and OpticsA possible solution could be to determine the analysis frequency based on the zero crossings and then multiply the acquired signal with sine and...10 replies | 357 view(s)
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Yesterday, 09:18U2 LED reversed, but I see what you mean. You should know. If circuit isolation is a safety feature, your present design may also conflict with...23 replies | 767 view(s)
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Yesterday, 08:34FvM replied to a thread Phase detector with synchronous logic (FPGA) in RF, Microwave, Antennas and OpticsThe 50 us limitation wasn't mentioned yet. In this case, "processing the entire dataset" is in fact more promising. Question is if you know the exact...10 replies | 357 view(s)
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17th February 2020, 23:11FvM replied to a thread 14 bit adc output to 5 bit data conversion in VHDL in PLD, SPLD, GAL, CPLD, FPGA DesignMay be the question is that trivial, may be some specific coding is intended. The OP missed to ask a clear question.3 replies | 295 view(s)
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17th February 2020, 23:03FvM replied to a thread Phase detector with synchronous logic (FPGA) in RF, Microwave, Antennas and OpticsThe multiply idea sketched in post #1 is basically good, but it should be extended to I/Q demodulation to work over 0 to 360 degree. You can either...10 replies | 357 view(s)
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17th February 2020, 13:51dpaul replied to a thread ISCAS 89-s38417 testbench required in ASIC Design Methodologies and Tools (Digital)I see the 'bench' files here http://www.pld.ttu.ee/~maksim/benchmarks/iscas89/bench/ also the core number you have listed. Was a simple google...2 replies | 231 view(s) -
17th February 2020, 13:05May be mathematically correct, but wrong in Z transform context.4 replies | 235 view(s)
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17th February 2020, 10:05Don't think so. U1 LED is driven with wrong polarity and has negative transistor supply. Many previously mentioned problems are still present,...23 replies | 767 view(s)
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17th February 2020, 09:33FvM replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA DesignA bit more complex. You'll design a kind of software PLL with 2 and 4 MHz output, locked to the 2 MHz reference. Dynamic phase shift might be used if...11 replies | 607 view(s)
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17th February 2020, 09:21High Voltage Coupling means what, exactly? Measuring current, voltage, linearly, which range? HCPL-0370 reference suggest you want to compare current...2 replies | 148 view(s)
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16th February 2020, 22:36If you experience contradicting hearsay specs, why not refer to major manufacturers datasheets instead?4 replies | 285 view(s)
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16th February 2020, 22:20I believe, you either don't read the answers or don't understand it. I have no other explanation for seeing the circuit in post #45 that has been...62 replies | 1335 view(s)
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16th February 2020, 13:39Incomplete problem description results in ambiguous or useless answer. At least one unclear point is floating substrate nodes. Transconductance...3 replies | 210 view(s)
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16th February 2020, 13:181/2 sample period is no meaningful quantity in sampled data system. Output is only observed at integer multiples of sampling period. You'll see if...4 replies | 235 view(s)
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16th February 2020, 13:01A symmetrical fault example, referring to your previous design. How would you detect it? - - - Updated - - - The file is different from...23 replies | 767 view(s)
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16th February 2020, 12:47I feel that some points should be sorted out. You have been originally asking how to amplify µV signal to mV, with minimal supply voltage. Later...62 replies | 1335 view(s)
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16th February 2020, 11:34The idea of an ungrounded network (IT network) is to avoid short circuit currents in case of a single ground fault while being able to detect the...23 replies | 767 view(s)
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16th February 2020, 10:26A RHP pole in the open loop transfer function can be only generated if the feedforward turns into positive feedback, likely to happen for the post #1...3 replies | 219 view(s)
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15th February 2020, 12:58FvM replied to a thread Waveform saving upon trigger in windows from Oscilloscope in Elementary Electronic QuestionsMSO2000B series has 1M data points memory, about 10 sec @ 100 kSPS. Timebase can be set up to 100 s/div, 1000 s total length with respective lower...5 replies | 295 view(s)
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15th February 2020, 12:15Your monitor circuit is generating huge leakage currents and power dissipation and surely no acceptable IMD solution. What is your of insulation...23 replies | 767 view(s)
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15th February 2020, 11:39FvM replied to a thread Waveform saving upon trigger in windows from Oscilloscope in Elementary Electronic QuestionsThe simple way to save the waveform is to set up acquisition parameters as required, make a measurement and save the waveform to USB drive in *.csv...5 replies | 295 view(s)
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14th February 2020, 15:45In case you want someone to check your transformer design, you should give complete information, e.g. which input voltage was used during the test....23 replies | 699 view(s)
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14th February 2020, 15:32Inrush current can be captured with a current probe and a digital oscilloscope. It's not clear what you exactly want to achieve and how the...3 replies | 208 view(s)
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14th February 2020, 09:48FvM replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA DesignPossible solutions have been sketched, but the application requirements are yet unknown.11 replies | 607 view(s)
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14th February 2020, 09:42IMD (insulation monitoring devices) are specified by IEC 61557 and available on the market. For unearthed (IT) power supplies, these devices are...23 replies | 767 view(s)
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14th February 2020, 09:27dpaul replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA DesignThe OP has posted the same Q in Xilinx forums yesterday and did not provide sufficient details in order to answer his Q. My answer to him would be...11 replies | 607 view(s)
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14th February 2020, 09:00FvM replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA Design10 MHz minimal clock input frequency is common series 7 MMCM spec as far as I'm aware of.11 replies | 607 view(s)
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13th February 2020, 18:08FvM replied to a thread how to generate 4MHz clock from 2 MHz clock. in PLD, SPLD, GAL, CPLD, FPGA DesignIf you have a higher frequency clock available, a digital PLL can generate the 4 MHz clock, however limited to the time resolution of the system...11 replies | 607 view(s)
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13th February 2020, 17:25Having already multi mV range offset: surely not.62 replies | 1335 view(s)
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