FvM
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Yesterday, 22:52Not sure if the display is designed to work with 4.3V single supply. The data sheet should tell. In any case, the circuit lacks a means to adjust Vee...3 replies | 63 view(s) -
Yesterday, 22:00I'm talking about the pin 8 current limiting resistor, you have confirmed its necessity in post #4. Ic/Ib ratio is a matter of appropriate...13 replies | 744 view(s)
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Yesterday, 19:00FvM replied to a thread [moved] How to design a crystall oscilator circuit using CMOS 40106 DESIGN in Hobby Circuits and Small Projects ProblemsI agree about unbuffered inverter. Other configuration like buffered inverter or ST inverter are likely to cause unstable operation or possibly...7 replies | 151 view(s)
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Yesterday, 15:08I guess, not particularly an IGBT simulation problem, but a problem with the specific model (too complex, weird equations, whatsoever). LTspice seems...12 replies | 402 view(s)
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Yesterday, 11:14dpaul replied to a thread HDMI in and out , just connected in to out. in PLD, SPLD, GAL, CPLD, FPGA DesignI have to understand what you are exactly doing. Is it like the following? Raspberry Pi HDMI o/p --> Virtex 4 --> HDMI out to display ...8 replies | 591 view(s) -
Yesterday, 09:33dpaul replied to a thread Synth. area reduced when adding a pipeline register in ASIC Design Methodologies and Tools (Digital)DC will generate a synth report. Have you investigated the DC generated reports in both cases? Your answer is likely to be there in the reports.....4 replies | 228 view(s)
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Yesterday, 09:26dpaul replied to a thread Spartan6 (ISE 14.7) how to generate differential clock? in PLD, SPLD, GAL, CPLD, FPGA DesignAn OBUFDS Xilinx primitive might suite your purpose. I would suggest you to read the realted "SelectIO Resources" docu for Series6 Xilinx FPGA for...5 replies | 195 view(s)
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Yesterday, 08:53Neither. The formula makes only sense for average Ic.12 replies | 402 view(s)
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22nd April 2019, 21:06FvM replied to a thread LM741 Bass/Treble & Volume Control in Hobby Circuits and Small Projects ProblemsUnfortunately not working, wrong bias of noninverting OP input.13 replies | 1184 view(s)
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22nd April 2019, 15:46I don't understand the exact purpose of the stimulator part, but I really don't need to know. You should however understand it if you are doing any...10 replies | 194 view(s)
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22nd April 2019, 15:27It may be no problem for this design, but I don't understand the purpose of thermal reliefs here. I won't use it. High resistor element working...4 replies | 279 view(s)
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22nd April 2019, 14:19I can't read a sense into sending the blood pressure signal to stimulation amplifier. What should be the purpose?10 replies | 194 view(s)
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22nd April 2019, 14:12FvM replied to a thread Spartan6 (ISE 14.7) how to generate differential clock? in PLD, SPLD, GAL, CPLD, FPGA DesignThe inverted signal is generated in IO cell, the usual way is to have one output signal (e.g. a top level port of your design) and assign a...5 replies | 195 view(s)
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22nd April 2019, 14:03FvM replied to a thread priority on two asynch triggered events in ASIC Design Methodologies and Tools (Digital)I checked with Quartus integrated synthesis, as expected the #7 code causes an error: The modified code according to post #10 can be compiled...13 replies | 890 view(s)
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22nd April 2019, 11:49Looks like multiple problems at once. - changing CREG: either antenna or power supply problem - garbage characters: UART problems, defective modem...13 replies | 775 view(s)
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22nd April 2019, 11:35FvM replied to a thread Spartan6 (ISE 14.7) how to generate differential clock? in PLD, SPLD, GAL, CPLD, FPGA DesignBy choosing a suitable differential output pin pair and the respective differential IO standard in constraint editor.5 replies | 195 view(s)
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22nd April 2019, 11:25If you use low local data rate (e.g. 1.2K) and allow the modem to negotiate an "intelligent" protocol with error correction and data compression, no...13 replies | 1286 view(s)
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22nd April 2019, 10:56Firstly, I don't understand why the arbitrary design change (M14 gate connection) from post #22 to post #23 was made? Any problem of the old circuit...28 replies | 1968 view(s)
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22nd April 2019, 10:42Current measurement can hardly act as a reliable fan operation monitor. Depending on the failure mode, the actual current may be any value between...28 replies | 1371 view(s)
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22nd April 2019, 10:28Do you want to use the pressure transducer with its dedicated amplifier, or include the amplifier function in your design? In the latter case, does...10 replies | 194 view(s)
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22nd April 2019, 10:09Before selecting suitable components and deciding about the layout, you need to fix the specification. impedance matching required for both...6 replies | 294 view(s)
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22nd April 2019, 09:44FvM replied to a thread priority on two asynch triggered events in ASIC Design Methodologies and Tools (Digital)I guess there's a typo in post #7. This construct complies with the register template and should work in functional simulation as well: assign...13 replies | 890 view(s)
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21st April 2019, 23:09FvM replied to a thread priority on two asynch triggered events in ASIC Design Methodologies and Tools (Digital)Your suggested construct doesn't comply with the synthesizable register template, I doubt that it will be accepted by synthesis tools. I don't yet...13 replies | 890 view(s)
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21st April 2019, 11:42Current sense may be reduced down to 0.2 if you want maximal output current, efficiency will probably drop.13 replies | 744 view(s)
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21st April 2019, 10:46FvM replied to a thread Help to make circuit for Nerve Stimulation Device in Hobby Circuits and Small Projects ProblemsThe "Amplipulse" designs gives at least an idea how a TENS instrument can be designed, the original DC current source approach is completely missing...24 replies | 6047 view(s)
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21st April 2019, 10:25I think, the potential catastrophes are foreseeable and can be avoided if you clearly plan ahead the intended function. It's straightforward to have...4 replies | 319 view(s)
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21st April 2019, 09:48180 ohm is the suggested value for 12V input and 1A Ipk. Read https://www.onsemi.com/pub/Collateral/AN920-D.PDF13 replies | 744 view(s)
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21st April 2019, 09:33FvM replied to a thread Biasing Circuit for LNA with Chebyshev Bandpass Filter in Analog Circuit DesignThe circuit isn't the equivalent of post #1 which connects L2/C2 to a low impedance node, so not surprising to get different S11 and kill the...6 replies | 439 view(s)
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21st April 2019, 09:24You should really read the documentation and understand what's appropriate according to the application and peer capabilities. Particularly I don't...13 replies | 1286 view(s)
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20th April 2019, 23:14I guess the library SPDT switches are CMOS switches with respective drivers. If you want similar performance, there's no more simple circuit...3 replies | 300 view(s)
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