FvM -

Today, 11:24

FvM replied to a thread Large signal cut off frequency of an OFA in Elementary Electronic Questions

You'll calculate slew rate for maximal frequency and output magnitude, then required OTA bias current.

3 replies | 63 view(s)

Today, 11:09

FvM replied to a thread Whats wrong with my full wave bridge rectifier in RF, Microwave, Antennas and Optics

I_PROBE device name suggests the latter. How did you try impedance matching? Presently we see a large series inductor L1 that's probably...

5 replies | 134 view(s)

Today, 10:59

FvM replied to a thread Eagle is being deliberately trashed in PCB Routing Schematic Layout software and Simulation

You can know who owns Autodesk, it's a market listed US corporation. The simple reason why they are implementing a subscription license model for...

10 replies | 356 view(s)

Today, 10:06

FvM replied to a thread Large signal cut off frequency of an OFA in Elementary Electronic Questions

The usual technical term for OP is large signal cut bandwidth or sometimes "power bandwidth" rather than large signal cut off frequency. In case of...

3 replies | 63 view(s)

Today, 09:59

FvM replied to a thread Switching power supply emission the electromagnetic waves in Power Electronics

Not necessarily. If you see FM interferences, it's more likely the computer main board, graphic card or display.

4 replies | 170 view(s)

Today, 09:53

FvM replied to a thread Difference of RF-Waveform between DSB-ASK and SSB-ASK in RF, Microwave, Antennas and Optics

The commonly understood technical terms for the shown modulation methods are ASK and BPSK. They are e.g. used in RFID standard documents. A...

2 replies | 67 view(s)

Yesterday, 23:34

FvM replied to a thread Transmit data by Connect two ADSL modems over copper telephone line up to 1KM in Digital communication

The electrical safety problem is beyond the original thread topic and also not fitting the digital communication section. You better start a new...

18 replies | 856 view(s)

Yesterday, 23:08

FvM replied to a thread Eagle is being deliberately trashed in PCB Routing Schematic Layout software and Simulation

Autodesk is a major CAD company but hadn't EDA products in the portfolio before acquiring Eagle. So the obvious reason why they changed the licensing...

10 replies | 356 view(s)

21st June 2018, 19:02

FvM replied to a thread OTA along with class AB output stage in Analog Circuit Design

That's what I say about the output stage. I still believe that it's essentially a drawing error because the MOS diode bias circuit makes no sense for...

18 replies | 305 view(s)

21st June 2018, 17:19

FvM replied to a thread Measured and simulated reflection coefficient s11 comparison in RF, Microwave, Antennas and Optics

Tracing it in a graphic tool?

3 replies | 78 view(s)

21st June 2018, 17:13

FvM replied to a thread RF signal of SPDT and Bandpass filter in RF, Microwave, Antennas and Optics

Filters in "RF circuits" (you didn't tell anything about your application except the frequency range) can be useful or even required for different...

4 replies | 110 view(s)

21st June 2018, 13:35

FvM replied to a thread [SOLVED] high voltage zener operation in Elementary Electronic Questions

Plus pulse absorption capability for dynamic behavior, e.g. withstanding to ESD events.

32 replies | 592 view(s)

21st June 2018, 07:43

FvM replied to a thread [SOLVED] high voltage zener operation in Elementary Electronic Questions

Zener diode voltage is linked to current by an I/V characteristic. To determine the maximum voltage that can be driven into a zener diode, you need...

32 replies | 592 view(s)

20th June 2018, 21:42

FvM replied to a thread OTA along with class AB output stage in Analog Circuit Design

It's no class AB output stage. You should place complementary common drain instead of common source output stage.

18 replies | 305 view(s)

20th June 2018, 21:29

FvM replied to a thread [SOLVED] high voltage zener operation in Elementary Electronic Questions

How is this statement related to the post #1 circuit und question? You didn't yet explain what's the problem behind this thread. What's the...

32 replies | 592 view(s)

20th June 2018, 10:58

FvM replied to a thread gyroscopes and LP filter in Analog Circuit Design

A second order Butterworth filter has -90 degree phase at the cut-off frequency (-3 dB point).

17 replies | 316 view(s)

20th June 2018, 09:42

FvM replied to a thread [SOLVED] high voltage zener operation in Elementary Electronic Questions

Makes even less sense. To get 50W power dissipation in the zener diode (about 4A zener current), you need to burn 200 kW in the current limiting...

32 replies | 592 view(s)

20th June 2018, 07:50

FvM replied to a thread gyroscopes and LP filter in Analog Circuit Design

Why "1/2 output", that's just a speculation without knowing the magnitude and phase characteristic. The relation will be different for each filter...

17 replies | 316 view(s)

20th June 2018, 07:41

FvM replied to a thread Puzzled by OPA and output noise in Analog Circuit Design

The waveform count doesn't fit, only 6 rather than 7 images attached. What's connected in place of VG2, a ground short? Are the OPA344 and...

7 replies | 193 view(s)

20th June 2018, 07:11

FvM replied to a thread [SOLVED] high voltage zener operation in Elementary Electronic Questions

A brief view on the zener diode I/V characteristic clarifies that this can't ever happen (at least not without blasting the zener diode chip before)....

32 replies | 592 view(s)

20th June 2018, 06:39

FvM replied to a thread How Carrier and Code NCO generates new frequency and phase? in PLD, SPLD, GAL, CPLD, FPGA Design

What do you mean with decimal representation in this regard? What's the range of the loop filter output? - - - Updated - - - The "mathematical...

4 replies | 136 view(s)

20th June 2018, 06:30

FvM replied to a thread Verilog code for BCD to Floating point representation in PLD, SPLD, GAL, CPLD, FPGA Design

A Verilog implementation of double dabble algorithm can be e.g. found here (didn't check the code)...

32 replies | 697 view(s)

19th June 2018, 16:41

FvM replied to a thread Doorbell needs to be stepped up to 24v for Ring, but what about solenoid in chime? in Analog Circuit Design

Can you show how you achieved 29A with 24V and 51 ohms (+ inductance) in your simulation?

14 replies | 401 view(s)

19th June 2018, 15:44

FvM replied to a thread transform simple low voltage OTL tube amp into lower impedance by paralleling tubes in Tubes and Retro

Individual cathode resistors, anode resistor should be scaled down according to # of tubes. In the Rout >> RL range, output voltage is roughly...

2 replies | 339 view(s)

19th June 2018, 15:17

FvM replied to a thread How Carrier and Code NCO generates new frequency and phase? in PLD, SPLD, GAL, CPLD, FPGA Design

In a typical NCO design, the phase increment is a multi bit frequency control word rather than a single bit stream. See...

4 replies | 136 view(s)

19th June 2018, 07:36

FvM replied to a thread [SOLVED] Half Wave Rectifier when input voltage is negative in Elementary Electronic Questions

Although rail-to-rail output is nearly a standard in general purpose OPs these days, you still have specialized devices that can't achieve it due to...

9 replies | 304 view(s)

19th June 2018, 07:30

FvM replied to a thread Verilog code for BCD to Floating point representation in PLD, SPLD, GAL, CPLD, FPGA Design

Regarding the text in "updated diagram", seems like you are repeating questions that have been already answered throughout this thread.

32 replies | 697 view(s)

19th June 2018, 07:28

FvM replied to a thread ozonated liquid material compatability in Miscellaneous Engineering

Actually asking about saturated solution (≈100 mg/l) ? Usual water sterilization concentrations as discussed in the quoted article are far below....

4 replies | 249 view(s)

19th June 2018, 02:40

syedshan started a thread Does an eNB knows the location of a UE in Digital communication

Hi all, In cellular communication, does the eNB knows the location of UEs it is serving. If yes, then what procedure does it follows?

0 replies | 206 view(s)

18th June 2018, 22:47

FvM replied to a thread Verilog code for BCD to Floating point representation in PLD, SPLD, GAL, CPLD, FPGA Design

Although the OP requested a factor of 1/4095, it's not necessarily the exact solution. Most 12-bit ADC have a quantization step of Vref/4096. If you...

32 replies | 697 view(s)

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