FvM -

Today, 10:58

FvM replied to a thread gyroscopes and LP filter in Analog Circuit Design

A second order Butterworth filter has -90 degree phase at the cut-off frequency (-3 dB point).

17 replies | 294 view(s)

Today, 09:42

FvM replied to a thread high voltage zener operation in Elementary Electronic Questions

Makes even less sense. To get 50W power dissipation in the zener diode (about 4A zener current), you need to burn 200 kW in the current limiting...

12 replies | 162 view(s)

Today, 07:50

FvM replied to a thread gyroscopes and LP filter in Analog Circuit Design

Why "1/2 output", that's just a speculation without knowing the magnitude and phase characteristic. The relation will be different for each filter...

17 replies | 294 view(s)

Today, 07:41

FvM replied to a thread Puzzled by OPA and output noise in Analog Circuit Design

The waveform count doesn't fit, only 6 rather than 7 images attached. What's connected in place of VG2, a ground short? Are the OPA344 and...

4 replies | 124 view(s)

Today, 07:11

FvM replied to a thread high voltage zener operation in Elementary Electronic Questions

A brief view on the zener diode I/V characteristic clarifies that this can't ever happen (at least not without blasting the zener diode chip before)....

12 replies | 162 view(s)

Today, 06:39

FvM replied to a thread How Carrier and Code NCO generates new frequency and phase? in PLD, SPLD, GAL, CPLD, FPGA Design

What do you mean with decimal representation in this regard? What's the range of the loop filter output? - - - Updated - - - The "mathematical...

4 replies | 118 view(s)

Today, 06:30

FvM replied to a thread Verilog code for BCD to Floating point representation in PLD, SPLD, GAL, CPLD, FPGA Design

A Verilog implementation of double dabble algorithm can be e.g. found here (didn't check the code)...

32 replies | 684 view(s)

Yesterday, 16:41

FvM replied to a thread Doorbell needs to be stepped up to 24v for Ring, but what about solenoid in chime? in Analog Circuit Design

Can you show how you achieved 29A with 24V and 51 ohms (+ inductance) in your simulation?

12 replies | 318 view(s)

Yesterday, 15:44

FvM replied to a thread transform simple low voltage OTL tube amp into lower impedance by paralleling tubes in Tubes and Retro

Individual cathode resistors, anode resistor should be scaled down according to # of tubes. In the Rout >> RL range, output voltage is roughly...

2 replies | 225 view(s)

Yesterday, 15:17

FvM replied to a thread How Carrier and Code NCO generates new frequency and phase? in PLD, SPLD, GAL, CPLD, FPGA Design

In a typical NCO design, the phase increment is a multi bit frequency control word rather than a single bit stream. See...

4 replies | 118 view(s)

Yesterday, 07:36

FvM replied to a thread [SOLVED] Half Wave Rectifier when input voltage is negative in Elementary Electronic Questions

Although rail-to-rail output is nearly a standard in general purpose OPs these days, you still have specialized devices that can't achieve it due to...

9 replies | 273 view(s)

Yesterday, 07:30

FvM replied to a thread Verilog code for BCD to Floating point representation in PLD, SPLD, GAL, CPLD, FPGA Design

Regarding the text in "updated diagram", seems like you are repeating questions that have been already answered throughout this thread.

32 replies | 684 view(s)

Yesterday, 07:28

FvM replied to a thread ozonated liquid material compatability in Miscellaneous Engineering

Actually asking about saturated solution (≈100 mg/l) ? Usual water sterilization concentrations as discussed in the quoted article are far below....

4 replies | 136 view(s)

Yesterday, 02:40

syedshan started a thread Does an eNB knows the location of a UE in Digital communication

Hi all, In cellular communication, does the eNB knows the location of UEs it is serving. If yes, then what procedure does it follows?

0 replies | 128 view(s)

18th June 2018, 22:47

FvM replied to a thread Verilog code for BCD to Floating point representation in PLD, SPLD, GAL, CPLD, FPGA Design

Although the OP requested a factor of 1/4095, it's not necessarily the exact solution. Most 12-bit ADC have a quantization step of Vref/4096. If you...

32 replies | 684 view(s)

18th June 2018, 18:03

FvM replied to a thread gyroscopes and LP filter in Analog Circuit Design

It certainly doesn't mean this, just say the low pass bandwidth is greater than 60 Hz.

17 replies | 294 view(s)

18th June 2018, 17:57

FvM replied to a thread Verilog code for BCD to Floating point representation in PLD, SPLD, GAL, CPLD, FPGA Design

First part of your answer (ADC result scaling to integer millivolt) has been already discussed in post #6 and #7. BCD conversion with /10 division...

32 replies | 684 view(s)

18th June 2018, 17:15

FvM replied to a thread [SOLVED] ltspice hierarchical circuit error in PCB Routing Schematic Layout software and Simulation

Why don't you start with the test circuit in post #5? The simulation runs with no errors.

10 replies | 283 view(s)

18th June 2018, 07:14

FvM replied to a thread 50/30 ohm coax adapter in RF, Microwave, Antennas and Optics

Minimum loss means 6.5 dB in this case. Is it acceptable for the application?

8 replies | 216 view(s)

18th June 2018, 07:01

FvM replied to a thread gyroscopes and LP filter in Analog Circuit Design

There are two motivations for the low pass: - reduce the gyroscope signal noise bandwidth and respective variance - filter out residuals of...

17 replies | 294 view(s)

18th June 2018, 06:57

FvM replied to a thread [SOLVED] ltspice hierarchical circuit error in PCB Routing Schematic Layout software and Simulation

The same .asc and .asy is already attached in my post. But you didn't show a circuit importing the Memory symbol. What's your problem at all?

10 replies | 283 view(s)

18th June 2018, 06:53

FvM replied to a thread Modifying an ATX power supply in Hobby Circuits and Small Projects Problems

The article is about converting an ATX device into a single output variable voltage supply. That should work under circumstances. But it's not...

4 replies | 188 view(s)

17th June 2018, 14:46

FvM replied to a thread IR2110 High Side Problem in Power Electronics

Nothing has been said about DC link voltage, SS34 (40 V schottky) can work for low voltage. But bootstrap capacitor of 100 nF works in no way for 50...

6 replies | 209 view(s)

17th June 2018, 14:38

FvM replied to a thread [SOLVED] ltspice hierarchical circuit error in PCB Routing Schematic Layout software and Simulation

I don't understand what your problem is. You can instantiate the symbol and connect it. Apparently a correct net list is generated. The best way...

10 replies | 283 view(s)

17th June 2018, 14:17

FvM replied to a thread adjustable voltage and current power supply in Power Electronics

In relation to the intended function (adjustable constant I/V power supply with switch mode pre-regulator), the circuit isn't overly complex at first...

14 replies | 372 view(s)

17th June 2018, 12:02

FvM replied to a thread Noise in CMOS Inverter in Analog Circuit Design

Which simulation circuit are you talking about? The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback...

32 replies | 1169 view(s)

17th June 2018, 11:34

FvM replied to a thread Noise in CMOS Inverter in Analog Circuit Design

Sounds like you have forgotten the thread questions in the meantime. The problem was to measure output impedance. You necessarily need to ground the...

32 replies | 1169 view(s)

16th June 2018, 08:46

FvM replied to a thread [SOLVED] what are the risks for isolating test equipment by negating earth ground in Elementary Electronic Questions

The idea of an isolation or safety transformer is to provide a supply voltage without earth connection. Respectively they are exposing the output...

9 replies | 320 view(s)

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