FvM
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Today, 10:50dpaul replied to a thread How do i read or write to ram address given in datasheet? using verilog in PLD, SPLD, GAL, CPLD, FPGA DesignAs mentioned above, you need to provide the bus info connecting the RAM. Then you need to drive those bus signals for READ or WRITE cases.2 replies | 57 view(s) -
Today, 08:19Doesn't sound bad in general, but some details aren't quite clear. Do you mind to share a CAD drawing of the intended sensor mount?1 replies | 61 view(s) -
Yesterday, 22:02FvM replied to a thread Operational amplifier driving capability test in Analog Integrated Circuit (IC) Design, Layout and FabricationThe described setup (setting a fixed output voltage) doesn't fully test "driving capability", you want to evaluate the available output current over...9 replies | 109 view(s)
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Yesterday, 18:33FvM replied to a thread Problem adding reset to master slave D-FF for phase detector in ASIC Design Methodologies and Tools (Digital)In a regular master slave FF, the asynchronous reset signal is expected to immediately reset both stages independent of the clock state, that's what...5 replies | 294 view(s)
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Yesterday, 16:03Individual harmonics have different limit values. THD isn't enough. As for the general question, FFT is supported by most modern digital scopes....10 replies | 685 view(s)
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Yesterday, 09:54FvM replied to a thread Higher Current Consumption than expected with AFE and embedded Flash in IoT - Internet of ThingsHard to give less information… Where do you see the current peak and when? You should be able to trace the current path down to the component...5 replies | 97 view(s)
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Yesterday, 09:31FvM replied to a thread [SOLVED] Suppressing the spacing in $fwrite command of Verilog in PLD, SPLD, GAL, CPLD, FPGA DesignReview System Verilog language reference, paragraph 21.2.1.3 Size of displayed data. It's regular C format specifier syntax, by the way.3 replies | 105 view(s)
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16th September 2019, 16:24It depends. Some thermal pastes with high thermal conductivity are metal filled and also electrically conductive. But as far as I can see from the...26 replies | 715 view(s)
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16th September 2019, 13:58FvM replied to a thread [SOLVED] AMS simulation of D-FF in Analog Integrated Circuit (IC) Design, Layout and FabricationThere's no clock signal fed to your circuit, respectively output is uninitialized.. Confusingly you are providing a multi level ("electrical")...2 replies | 129 view(s)
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16th September 2019, 12:59The order of magnitude sounds reasonable. Obviously the numbers have been empirically validated, but your antenna geometry may be different. You...8 replies | 388 view(s)
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16th September 2019, 10:25Adjustment is either at the probe or the probe connector. Why don't you read the manual?26 replies | 715 view(s)
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15th September 2019, 15:10FvM replied to a thread Is there possibility to force a filter topology in DA_LClowpassMatch in ADS? in RF, Microwave, Antennas and Opticsfrdm90 didn't yet release a matching bandwidth specification. I presume, it's not possible to achieve a higher bandwidth with LC network for the...24 replies | 699 view(s)
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15th September 2019, 13:53Besides unsuitable probe connection it may be dropping DC supply. I won't care about it much. Overshoot is much more a problem. It probably kills the...26 replies | 715 view(s)
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15th September 2019, 12:53How can you measure with different ground connection for blue and yellow trace simultaneously? The real circuit must be somehow different. - - -...26 replies | 715 view(s)
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15th September 2019, 11:56No. I referred to the isolation capacitance, e.g. the transformer interwinding capacitance. The linear voltage regulator circuit is O.K. But it's not...26 replies | 715 view(s)
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15th September 2019, 09:55O.K., you can tune a diff mode filter to reject a particular frequency, at cost of wideband suppression. If it helped in a special case, it's surely...14 replies | 2122 view(s)
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15th September 2019, 09:48There's no DC bus in a "direct converter", which constitutes already some of the circuit problems. It's not clear where you measure the "IGBT...26 replies | 715 view(s)
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14th September 2019, 16:23Part of your points have been already discussed in the previous thread. Surely not. A choke has maximal impedance at it's SRF, respectively...14 replies | 2122 view(s)
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14th September 2019, 11:46FvM replied to a thread Problem adding reset to master slave D-FF for phase detector in ASIC Design Methodologies and Tools (Digital)I don't understand what you consider "wrong" in the posted simulation waveforms. I don't recognize missing pulses or similar artefacts. Please...5 replies | 294 view(s)
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14th September 2019, 09:49Sure, but the problem is at least of theoretical interest. Kajunbee's empirical observation that braking the precession slows down the gyro rotation...25 replies | 673 view(s)
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13th September 2019, 16:04FvM replied to a thread Problem adding reset to master slave D-FF for phase detector in ASIC Design Methodologies and Tools (Digital)What did you observe?5 replies | 294 view(s)
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12th September 2019, 21:17Why do you think the number of transition could be limited in off-chip mode?1 replies | 171 view(s)
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12th September 2019, 21:00Ferromagnetic materials are bad conductors for high frequent AC. Not due to "hysteresis" but due to effect of permeability on skin depth. See e.g....3 replies | 214 view(s)
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12th September 2019, 13:47dpaul replied to a thread Facing some error in Verilog HDL coding of Standard deviation calculation? in PLD, SPLD, GAL, CPLD, FPGA DesignAll Verilog constructs should work within a file marked .sv. But the opposite is not true.9 replies | 370 view(s)
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12th September 2019, 07:31You'll determine the antenna impedance by measurement or simulation, then design the matching circuit.8 replies | 388 view(s)
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11th September 2019, 12:00dpaul replied to a thread Implementation of a MUX for selecting from 2 different sets of inputs in PLD, SPLD, GAL, CPLD, FPGA DesignSounds like a stages of MUXes...... As others have pointed out, a diagram is needed.5 replies | 247 view(s)
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