FvM
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Today, 00:46FvM replied to a thread Verilog shifter synthesis in Design Compiler in PLD, SPLD, GAL, CPLD, FPGA DesignYou are asking about constant or variable shift amount?2 replies | 71 view(s) -
Today, 00:42FvM replied to a thread ESD problem solved by using aluminium covered floor tiles? in Elementary Electronic QuestionsI see two problematic points. 1. You are reporting parts of the floor being covered with aluminium foil but no overall ESD flooring. 2. Apparently...16 replies | 131 view(s)
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Today, 00:23FvM replied to a thread Low and High Frequnecy Response in Analog Integrated Circuit (IC) Design, Layout and FabricationBy sketching and analysing the equivalent circuit of the amplifier. No, no. The first and second stage clearly constitute separate poles (at...8 replies | 233 view(s)
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Yesterday, 15:48"(vcom-1484) Unknown formal identifier" indicates that the LHS of a port association in the instantiation doesn't exist. The error message is the...5 replies | 143 view(s)
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Yesterday, 14:07FvM replied to a thread How to implement a transfer function with discrete components in Analog Circuit DesignYes, that's what the circuit implements.13 replies | 359 view(s)
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Yesterday, 12:44The shown simulation circuit is surely not working. Floating DIN, continuous SCLK, that's not how the device can be operated. Review datasheet...2 replies | 175 view(s)
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Yesterday, 11:34FvM replied to a thread How to implement a transfer function with discrete components in Analog Circuit DesignObviously. Can be implemented with basic active circuit.13 replies | 359 view(s)
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15th February 2019, 16:38FvM replied to a thread Any good optocoupler IC for voltage sensing with single voltage source in Power ElectronicsThe question makes sense if it refers to ACPL series of isolation amplifiers and sigma-delta modulators. However there's none with built-in power...3 replies | 163 view(s)
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15th February 2019, 12:27The OP claimed the filter should "not change the phase till 25-30kHz", see the discussion in my previous post #21. If we take this serious,...46 replies | 706 view(s)
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15th February 2019, 10:01Yes, the f0=40 kHz, Q=0.5 block can work well for 6th order Butterworh with 40 kHz cut-off. But Butterworth doesn't meet the linear phase requirement...46 replies | 706 view(s)
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15th February 2019, 09:49"The delay" in the present code doesn't change the trigger time. Triac trigger pulse must be delayed relative to zero crossing. And you need a zero...19 replies | 1297 view(s)
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14th February 2019, 23:02FvM replied to a thread Looking for BJT that has very low collector leakage current. in Analog Circuit DesignWould you mind to tell target leakage, capacitance and voltage numbers?3 replies | 109 view(s)
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14th February 2019, 22:47Besides ambiguous phrasing, I don't get the idea behind reusing the post #1 bi-quad block in a higher order filter. The specific complex pole pair...46 replies | 706 view(s)
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14th February 2019, 22:22Not sure if the poster shares your sense of humour. Anyway, I agree that the coding style should be avoided. Editing is only enabled 30 minutes...7 replies | 176 view(s)
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14th February 2019, 00:35Many people, I presume, including myself. But I guess, you wanted to ask if anyone has a working CDR circuit based on 4046?12 replies | 821 view(s)
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14th February 2019, 00:22If adapting signal levels to the SC filter range is your only problem, you are really a lucky guy. That's an - excuse me - almost trivial problem....17 replies | 335 view(s)
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13th February 2019, 18:04The circuit in post #1 doesn't implement a Bessel filter, it's roughly a critically damped (Q = 0.5) filter, very droopy as already stated. Looking...46 replies | 706 view(s)
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13th February 2019, 13:34A state-variable filter can act as bi-quad building block. https://en.wikipedia.org/wiki/State_variable_filter Potentiometers connected before Rf1...17 replies | 335 view(s)
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13th February 2019, 13:27FvM replied to a thread What does the LOOP GAIN's phase and gain margin say about the CLOSED LOOP response? in Analog Circuit DesignNo. GM holds more or less the same information as PM. See previous answer by sutapanaki. For simple amplifier characteristics, e.g. integrator...5 replies | 345 view(s)
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13th February 2019, 12:58Instead of "0 to 10 kHz" you should give a feasible frequency range specification. A 4th order filter that keeps characteristic over frequency range...17 replies | 335 view(s)
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13th February 2019, 09:36Cut-off frequencies are not always calculated for -3 dB (half power point) attenuation. The Okawa tool apparently uses -6dB point, which explains the...46 replies | 706 view(s)
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12th February 2019, 18:49A 4th order transfer function can be decomposed into two 2nd order function, the same with higher order filters. Filter design tools do already...46 replies | 706 view(s)
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12th February 2019, 11:13Using T1OSC with a 32 kHz watch crystal is the next best solution, however PIC16F877 has not low power features to operate the RTC battery powered....4 replies | 139 view(s)
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12th February 2019, 11:05FvM replied to a thread how to install workloads of C++ tools in the Visual Studio 2017 Express in Software Problems, Hints and ReviewsYou are asking about std::cout? Did include the respective header <iostream>?1 replies | 236 view(s)
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10th February 2019, 22:33Metal tubes are the usual choice.4 replies | 179 view(s)
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10th February 2019, 22:08Why do you think so?4 replies | 202 view(s)
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10th February 2019, 21:59It's not feasible with FPGA, it has neither analog switch features nor an USB 2.0 PHY. Besides MAX4999, there's a number of high speed analog signal...1 replies | 134 view(s)
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10th February 2019, 12:26FvM replied to a thread Question about electric and magnetic Hertizian dipoles in RF, Microwave, Antennas and OpticsSymmetry considerations seem to contradict your assumption at first sight. In any case phase and magnitude relation of both sources matter for the...2 replies | 137 view(s)
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10th February 2019, 12:22I suspect that unsuitable feedback loop compensation is causing the observed instability. By connection a capacitor to comp pin you get pure I...6 replies | 204 view(s)
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