FvM
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Today, 11:20FvM replied to a thread 50 ohm Dummy Load With 50dB Attenuator in RF, Microwave, Antennas and OpticsR1 to R4 placement is near to a star topology, but with inappropriate stub impedances. Problem is that you can't micro strip lines above 125 to...7 replies | 168 view(s) -
Today, 10:57Either your assumptions about 5 ns pulse risetime are wrong or they are using unnecessary large bandwidth. What's the objective of your...12 replies | 449 view(s)
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Today, 09:49FvM replied to a thread 50 ohm Dummy Load With 50dB Attenuator in RF, Microwave, Antennas and OpticsIdeally yes, but any real layout has non-zero dimensions and respectively some parasitic elements. A star topology should use Z=250 ohm strip...7 replies | 168 view(s)
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24th May 2020, 23:25To decide if a LED is suited for direct drive by a 3.3V microprocessor, you'll check it's forward voltage at the expected low mA current. Some LEDs...7 replies | 370 view(s)
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24th May 2020, 23:11FvM replied to a thread Relative sensitivity of various electronics components to ESD damage? in Elementary Electronic QuestionsExpect that manufacturers give specification, either in datasheet or general product documentation. Most of the mentioned devices have such a...1 replies | 138 view(s)
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24th May 2020, 11:55How do you know that specifically the HS driver is "blowing"? Sure that the MOSFETs are still healthy? There are several possible circuit issues, too...6 replies | 308 view(s)
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24th May 2020, 11:41FvM replied to a thread Measuring voltage drop across a diode in a switching circuit in Elementary Electronic QuestionsThat's voltage with zero output current - irrelevant. Instead of assuming an idealized current independent 0.7V voltage drop, you want to look for...6 replies | 329 view(s)
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24th May 2020, 11:15FvM replied to a thread Time Interleaved ADC Filtering at Output in Analog Integrated Circuit (IC) Design, Layout and FabricationTo simulate dynamic mismatch and its possible compensation, you need 1. a mismatch model, e.g. specified as acquisition bandwidth and sampling time...3 replies | 329 view(s)
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24th May 2020, 11:03I understand that "intermediate" temperatures come into play if you are e.g. using Peltier coolers instead of LN2. I don't know about specific...8 replies | 499 view(s)
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24th May 2020, 10:48FvM replied to a thread Variable Resistor clamping and output behaviour for LM2596-ADJ in Power ElectronicsI guess, the wrong R1 connection has been brought up by the unusual datasheet schematic layout. Yes. The datasheet has values for dropout...4 replies | 271 view(s)
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24th May 2020, 10:23Although Rb doesn't directly limit the peak base current, it clearly plays a role in setting it. As average current through C is zero, the average...5 replies | 421 view(s)
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24th May 2020, 09:51Read the Arduino library help thoroughly, no reason to fly blind. SPI speed isn't critical with AVR, no chance to exceed the ADF maximum. ...4 replies | 352 view(s)
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24th May 2020, 09:36FvM replied to a thread Measuring voltage drop across a diode in a switching circuit in Elementary Electronic QuestionsPeak value 7.7V - min or max value?6 replies | 329 view(s)
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23rd May 2020, 17:16FvM replied to a thread Will a filter block this waveform? in Hobby Circuits and Small Projects ProblemsReviewing the thread from the start, I don't know if you are asking about a 40 or 100 MHz crystal oscillator? Modulation has been mentioned, but...25 replies | 650 view(s)
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23rd May 2020, 17:06FvM replied to a thread Need for safe phase margin when dealing with sin input signals in Analog Integrated Circuit (IC) Design, Layout and FabricationAs already stated 45 degree phase margin will be accompanied by gain peaking in closed loop response. If it's no problem in your application, you can...8 replies | 325 view(s)
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22nd May 2020, 14:44DDR logic doesn't use dual-edge triggered FFs but separate FFs triggered by rising and falling edge.6 replies | 311 view(s)
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22nd May 2020, 12:31Wiznet has published example software, e.g. for AVR and STM32. You can use it as a template for your PIC18 design, just replacing the low level SPI...2 replies | 196 view(s)
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22nd May 2020, 12:23You may call it a device specific problem. But a very general problem if you don't find any logic device that has double edge sensitive FFs. As you...6 replies | 311 view(s)
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22nd May 2020, 12:17Because you can only synthesize circuit descriptions that are supported by the target hardware. No modern FPGA supports double clock edges. You...6 replies | 311 view(s)
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22nd May 2020, 12:13FvM replied to a thread Avoiding Ground Loop With Multiple Inputs to DAQ Board in Analog Circuit DesignI see inconsistencies in the specification that make it hard to answer your questions. You are initially talking about "DC to a few MHz" (post #4)...10 replies | 520 view(s)
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22nd May 2020, 11:44Obviously a current mirror biasing the emitter follower. Missing -VCC label at diode cathode.5 replies | 249 view(s)
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22nd May 2020, 08:45dpaul replied to a thread Implementation error (ERROR: Place: 1500) on ISE 14.5 in PLD, SPLD, GAL, CPLD, FPGA DesignRead this - https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_constraints_entry_methods.htm4 replies | 366 view(s) -
21st May 2020, 23:01FvM replied to a thread Serial Monitor to check feedback of GSM Sim900a in PC Programming and InterfacingO.k., according to the table, 8 MHz works too. But not with the settings used in your code. For debugging of serial interfaces, I prefer a dual...9 replies | 580 view(s)
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21st May 2020, 22:33Because it's closed loop hall sensor. LEM has good explanation of operation principle. Depending on your accuracy requirements, there are smaller and...3 replies | 208 view(s)
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21st May 2020, 13:29The simple answer is, most datasheets don't have detailed data necessary to extract the questioned SPICE model parameters.34 replies | 1496 view(s)
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21st May 2020, 12:35FvM replied to a thread Serial Monitor to check feedback of GSM Sim900a in PC Programming and InterfacingIt's not possible to achieve 115k baud rate with 16F887 and 8MHz crystal. Review baud rate table in datasheet. Select a lower baud rate or a...9 replies | 580 view(s)
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20th May 2020, 18:55You are trying to make a linear balanced modulator at a carrier level that operates the diodes as on-off switches? Is this possible at all?12 replies | 525 view(s)
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20th May 2020, 16:38The linked application note is specifically discussing CRC usage to verify code integrity in safety related applications. You have apparently a...2 replies | 218 view(s)
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20th May 2020, 16:26FvM replied to a thread Verilog and VHDL noise modelling in Analog Integrated Circuit (IC) Design, Layout and FabricationYour question isn't very specific, what do you want to achieve? VHDL and Verilog are digital simulators without means to represent analog signals...5 replies | 324 view(s)
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20th May 2020, 16:15FvM replied to a thread Determining Value of Capacitor Between PV Panel and DC-DC Convertor. in Power ElectronicsI would expect a bypass capacitor to be part of the DC/DC converter, so that input voltage ripple is reduced to an acceptable level without relying...6 replies | 353 view(s)
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