FvM
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Today, 09:13dpaul replied to a thread Creating verilog define for filename based on input file path, string concatenation in PLD, SPLD, GAL, CPLD, FPGA DesignWhat happens if you use the absolute path inside the RTL?2 replies | 14 view(s) -
Today, 09:09I don't use Matlab! So I jst gave the basic idea of using scripts. Now if it can be done in Matlab, good for the OP.5 replies | 114 view(s)
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Today, 06:46FvM replied to a thread CMRR is less than the DC differential gain in Analog Integrated Circuit (IC) Design, Layout and FabricationIn line with the fully differential amplifier threads you have posted during the last months, I assume that your amplifier will be operated with...6 replies | 84 view(s) -
Yesterday, 19:37FvM replied to a thread How to build current source based on modified Hawland current pump for 150 mA? in Analog Circuit DesignVarying R5 is not feasible if you want current source characteristic. The equations for Howland current source have been frequently discussed at...2 replies | 90 view(s)
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Yesterday, 16:21Just write a script in your fav scripting language (Bash, Perl, Python) which will read the txt file you have posted and write out the desired file...5 replies | 114 view(s)
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Yesterday, 15:11FvM replied to a thread ModelSim is not reporting errors properly in Software Problems, Hints and ReviewsModules are compiled separately, the error will pop up when you simulate (.e.g module "not bound" error). That's how the simulator works. There will...3 replies | 125 view(s)
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Yesterday, 09:48Hello OP, This looks like an internal module design to me. At the peripheral you don't have these many signals. If you provide us the project...9 replies | 232 view(s)
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Yesterday, 09:44It is Xilinx Design Constraint (.xdc) not "Vivado Timing Constraint ", which constrains the FPGA design as stated above. Read the latest version of...2 replies | 96 view(s)
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Yesterday, 08:54FvM replied to a thread can boost converters cause gate loop ringing in Elementary Electronic QuestionsTo discuss "gate loop" ringing, we should look at the gate driver circuit, not a boost converter data sheet.4 replies | 129 view(s)
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Yesterday, 08:46Returning from a journey, I see that the layered capacitance calculation fault this thread is based on still hasn't been corrected. You have...28 replies | 532 view(s)
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Yesterday, 08:05I fear you are reading too much into the problem. Too me it looks like a trivial FPGA exercise, unfortunately compiled with a too small device, e.g....9 replies | 232 view(s)
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16th June 2019, 22:44FvM replied to a thread How to move metal elements via magnetic waves? in Hobby Circuits and Small Projects ProblemsNone of the answers seemed to refer to the requirement to move the metal parts by an apparatus at least 1m apart. This is impossible if we sort out...8 replies | 310 view(s)
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16th June 2019, 22:19FvM replied to a thread Response of the TLINE for different frequencies and lengths in RF, Microwave, Antennas and OpticsI agree that the relation between electrical length and input impedance are presented correctly in the diagrams. You should be able to see in in a...11 replies | 211 view(s)
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15th June 2019, 23:16FvM replied to a thread Error loop must terminate within 10,000 iterations (vhdl) in PLD, SPLD, GAL, CPLD, FPGA DesignNo, Altera/Intel doesn't support textio for memory initialization. But that's not my point. The typical VHDL test bench code starts with a non...5 replies | 217 view(s)
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15th June 2019, 17:54The chips have different memory organisation and mostly different command sets. Although you can find access methods common to both devices, It's...1 replies | 110 view(s)
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15th June 2019, 17:11Maybe an ambiguousity of the term air gap, I mean air actually. I'm assuming that the space between electrode plates won't be completely filled with...28 replies | 532 view(s)
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15th June 2019, 06:43FvM replied to a thread Error loop must terminate within 10,000 iterations (vhdl) in PLD, SPLD, GAL, CPLD, FPGA DesignWe can surely discuss how to write synthesizable memory initialization. But this is pure test bench code.5 replies | 217 view(s)
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15th June 2019, 06:38FvM replied to a thread Best Solution to use DOT POINT by REVERSING 3rd. one Digit of 4-digit seven segment in MicrocontrollersWhy not simply rewire the segments instead of writing software?6 replies | 278 view(s)
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15th June 2019, 06:311 mm air gap? As a starting point, did you calculate the total effective Er of a combination of Er=1 and Er=1k or even 1000k?28 replies | 532 view(s)
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15th June 2019, 06:17You never mentioned IC design, just designing a circuit. I asked about the intended technology but the question wasn"t answered. It was obvious to me...49 replies | 702 view(s)
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14th June 2019, 14:46There's no problem with longer pulses, you seem not to understand the circuit operation. Suggest to perform a simulation. Please report if you see...49 replies | 702 view(s)
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14th June 2019, 14:24The RC delay solution has the problem that the extension time reduced for short negative pulses because the capacitor isn't fully discharged. This...49 replies | 702 view(s)
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14th June 2019, 14:15FvM replied to a thread Rational Approximation of Gaussian LPF in RF, Microwave, Antennas and OpticsNuhertz Filter Solutions does a good approximation, slightly lower pole pair Q than Bessel, unfortunately I have no access right now.2 replies | 109 view(s)
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14th June 2019, 13:32I don't think that rotating variable capacitor with high Er is feasible. The capacitance would be more defined by the unavoidable air gap than the...28 replies | 532 view(s)
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14th June 2019, 13:24FvM replied to a thread Audio amplifier on PCB error. Ports of opAmp shorted.Can't find the reason why? in Analog Circuit DesignHigh speed and power OPs without bypass capacitors are likely to self-oscillate. Also floating inputs may cause problems. You can e.g. connect the...10 replies | 258 view(s)
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14th June 2019, 10:44My apology for continuing a discussion that should be better carried on in the About Edaboard section. The "time to edit" limit was reduced to 30...4 replies | 202 view(s)
About FvM
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