FvM
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Today, 00:08In addition to what's already said, I would doubt that Vrms is the quantity of interest. I think, it's rather magnitude of the fundamental. Harmonic...6 replies | 95 view(s) -
Yesterday, 23:50The question doesn't make sense. Dual and quad SPI functions are only relevant to increase the interface throughput with SPI masters that support...2 replies | 96 view(s)
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Yesterday, 15:11The fault is probably not in the part of the code you are yet showing.6 replies | 84 view(s)
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Yesterday, 14:50Presume you know that flash memory area must be erased before writing to it.6 replies | 84 view(s)
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Yesterday, 14:44Unfortunately, the Ltspice model for Linear devices use a proprietary binary format and can't be used in other Spice tools.7 replies | 111 view(s)
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14th December 2018, 23:51Beside all other possible problems, you need an oscilloscope with 500 MHz, better 1 GHz bandwidth and a suitable probe (active or resistive) to...6 replies | 121 view(s)
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14th December 2018, 09:53dpaul replied to a thread What are some effective ways to create a self checking Testbench without ref model in PLD, SPLD, GAL, CPLD, FPGA DesignWhat do you mean by a "reference model". A TB should be such that it drives the DUT inputs such that the DUT functionality and stability is...2 replies | 167 view(s) -
13th December 2018, 22:12How about a variable current source?5 replies | 135 view(s)
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13th December 2018, 14:00Why do you assume that the "loop" serves a useful purpose?6 replies | 159 view(s)
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13th December 2018, 13:36Are you sure the chip is generating transducer excitation signals with correct frequency and the launch series resistors are matching the transducer...3 replies | 110 view(s)
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12th December 2018, 22:57The answer depends on the operation frequency.3 replies | 186 view(s)
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12th December 2018, 19:07The numbers mentioned in post #1 don't fit usual cable dimensions, except for the overall diameter. 24 AWG cable has cross section of about 0.22...5 replies | 256 view(s)
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12th December 2018, 17:35No, why? Particularly not a buffer in front of the OTA block. I believe, you have answered the question yourself. The input stage current is...6 replies | 178 view(s)
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12th December 2018, 09:29dpaul replied to a thread Transfer Data from DDR3-PL to BRAM using Zynq on ZC706 in PLD, SPLD, GAL, CPLD, FPGA DesignDo you have a test-bench for your design? Even if the design is complex, I would suggest you to build one. Many design bugs are caught and...4 replies | 358 view(s)
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11th December 2018, 18:00FvM replied to a thread Free trial of Altium designer 18.1.7 in PCB Routing Schematic Layout software and SimulationNo. Use "reports/measure distance" or ctrl-m. Similarly any function you are asking for can be found within a few clicks. Better work through a...7 replies | 321 view(s)
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11th December 2018, 12:37You have to expect strong frequency dependence of permittivity and resistivity. A detailed discussion can be found in Snelling Soft Ferrites. See...2 replies | 459 view(s)
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11th December 2018, 11:32Read time differences are small and probably irrelevant compared to SPI throughput limitations. Write time differences however matters a lot.5 replies | 231 view(s)
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10th December 2018, 17:59FvM replied to a thread Ceramic capacitor leakage current at 50 degC in Elementary Electronic QuestionsO.K., with very low sampling rate, the ADC input charge error can be neglected. But you still have some input leakage current.5 replies | 242 view(s)
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10th December 2018, 12:29FvM replied to a thread Ceramic capacitor leakage current at 50 degC in Elementary Electronic QuestionsDoes "Mikro ADC" refer to an unbuffered microcontroller (e.g. PIC) analog input? There will be considerable error due to ADC input current, capacitor...5 replies | 242 view(s)
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10th December 2018, 11:45FvM replied to a thread Xilinx XPower Analyzer Confidence Level in PLD, SPLD, GAL, CPLD, FPGA DesignThe table shows near to zero logic utilization, respectively no relevant dynamic power. You must know if this is realistic.4 replies | 291 view(s)
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9th December 2018, 18:03Not clear which effect you are asking about. Presuming voltage independent capacitance, which is roughly achieved by most capacitors, stored charge...13 replies | 548 view(s)
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9th December 2018, 17:47There's no pin definition. mini LVDS is an IO standard, not a specific interface. It's particularly intended to design internal interfaces of a...3 replies | 188 view(s)
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9th December 2018, 09:32The biggest problem for an accurate impedance measurement during in-circuit test will be the open SMA stub. For an exact measurement, there are...10 replies | 495 view(s)
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8th December 2018, 17:53FvM replied to a thread Number of layers available in diptrace? in PCB Routing Schematic Layout software and SimulationAs said, this is wrong.4 replies | 272 view(s)
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8th December 2018, 15:04FvM replied to a thread Number of layers available in diptrace? in PCB Routing Schematic Layout software and SimulationI'm not aware of any PCB tool on the market absolutely restricted to two layers. DipTrace of course isn't, the very first example on their website...4 replies | 272 view(s)
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8th December 2018, 14:42It's not. Current density for 1.6 kVA transformer (e.g. EI 195c) should be below 1.5 A/mm².4 replies | 165 view(s)
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8th December 2018, 10:22"measure return loss between two pads on my pcb" is equivocal in several regards. - singled ended or differential port? - nominal impedance -...10 replies | 495 view(s)
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8th December 2018, 09:52Any reason you designed an isolation transformer rather than an auto transformer? You can safe 65% of transformer power. I presume, you have...4 replies | 165 view(s)
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6th December 2018, 22:07FvM replied to a thread Difference between a two section tline and a single stub? in RF, Microwave, Antennas and OpticsLook thoroughly at the drawing. One side of the "main line" is terminated with Z0, the other with an arbitrary impedance ZL which has to be matched...7 replies | 372 view(s)
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