FvM
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Today, 10:10There's absolutely no reason to expect OP oscillations in this circuit. Depending on the nature of the input signal fed to the circuit, you...15 replies | 380 view(s) -
Yesterday, 13:20Did you follow the suggestions to remove everything from receive ISR that doesn't belong there? Particularly sending multiple UART characters?8 replies | 157 view(s)
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Yesterday, 13:08O.K., I see. I don't think there are so many 3 phase IGBT drivers with built-in soft shut down, e.g. not the devices linked in post #2. ...5 replies | 173 view(s)
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Yesterday, 12:07The SDR receivers are essentially DVB-T sticks and not designed for standalone operation. Besides lack of a nonvolatile configuration they also don't...5 replies | 171 view(s)
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Yesterday, 11:4247n or 100 nF/275 VAC X2 capacitors from major manufacturers are starting below 50 cent, single quantity at catalog distributors. Snubbering the...21 replies | 465 view(s)
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Yesterday, 11:16FvM replied to a thread MCPCB which is double sided and with plated through vias in Power Electronics8 mil/0.2 mm clearance is industry standard with 2 oz copper, works well for TSSOP packages down to 0.5 mm pin spacing. Wiring density is...11 replies | 212 view(s)
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18th January 2019, 22:59I see many papers explaining bump linearization in detail. You may also visualize it's working in a simulation. To give the basic idea, a...3 replies | 162 view(s)
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18th January 2019, 22:42Lossless integrator H(s) = 1/s, lossy integrator H(s) = 1/(s + a) In words, ideal integrator versus first order low pass1 replies | 59 view(s)
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18th January 2019, 17:42What do you exactly mean with "soft turn off function"?5 replies | 173 view(s)
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18th January 2019, 17:40Do I understand right that the problem also occurs with FRC clock source. Then it's surely no crystal oscillator problem. If you are already...9 replies | 153 view(s)
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18th January 2019, 12:16Consider that edge sensitive flip flops are usually implemented as master slave topology circuit.6 replies | 145 view(s)
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17th January 2019, 23:21I presume the output of the shown sensor arrangement can be transformed to cartesian xyz coordinates by a linear operation. A signal that represents...3 replies | 203 view(s)
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17th January 2019, 11:46That's a rather trivial interpretation, only based on the external waveforms shown in the simulation. You need to look at internal voltages and...5 replies | 178 view(s)
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16th January 2019, 22:25FvM replied to a thread USB differential pair on 2 layer board in Hobby Circuits and Small Projects ProblemsI have no impedance calculator at hand right now, but 40 miles trace width doesn't sound far off. It depends on the minimal clearance that can be...3 replies | 230 view(s)
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16th January 2019, 17:23Most PLC systems have either built-in or optional network interfaces and provide different protocols as server or client. What is your PLC system,...4 replies | 247 view(s)
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16th January 2019, 10:09FvM replied to a thread MCPCB which is double sided and with plated through vias in Power ElectronicsI see that the LEDs are populating only a small part of the top side, thus a heat spreading feature may be helpful. The through plated double side...11 replies | 212 view(s)
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16th January 2019, 09:59I have used 1/4 W metal film resistors (0207 axial package) and 1/2 W in more rugged designs. Not absolutely necessary.21 replies | 465 view(s)
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16th January 2019, 09:44Crystal models have been posted along with oscillator circuits in the Yahoo Ltspice forum https://groups.yahoo.com/neo/groups/LTspice/info mostly by...1 replies | 74 view(s)
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16th January 2019, 09:40I'm using the parametric search https://www.microchip.com/ParamChartSearch/Chart.aspx?branchID=300482 replies | 123 view(s)
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15th January 2019, 12:48The stimulation signal timing is the same, but the required reset setup time is obviously different.5 replies | 178 view(s)
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15th January 2019, 09:24dpaul replied to a thread ISE Project navigator while implementation is turned off in PLD, SPLD, GAL, CPLD, FPGA Design@OP, I think your OS is the issue. Read this AnswerRecord from Xilinx: https://www.xilinx.com/support/answers/18419.html None of the ISEs...7 replies | 393 view(s) -
15th January 2019, 08:05FvM replied to a thread MCPCB which is double sided and with plated through vias in Power ElectronicsThanks for clarification. I didn't yet see this kind of double sided MCPCB. So they manage to isolate the vias from the metal core somehow. Two...11 replies | 212 view(s)
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15th January 2019, 07:55Both simulations are different regarding DFF propagation delay and reset input setup time. We don't know which parameters you put in.5 replies | 178 view(s)
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14th January 2019, 22:20FvM replied to a thread MCPCB which is double sided and with plated through vias in Power ElectronicsWhat should be the purpose of metal cladding with your board? How can it connect to a heatsink? Multilayer MCPCB can be made, although not so common....11 replies | 212 view(s)
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14th January 2019, 18:01It's obviously a burglar alarm device, indicated by the tamper switch. 15 min delay sounds very unusual for burglar alarm, are you using it for a...6 replies | 172 view(s)
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14th January 2019, 17:33The R value is reasonable 2.2nF. Y2 capacitor won't give much snubber effect, better use X capacitor with 47 nF or 100 nF capacitance. - - -...21 replies | 465 view(s)
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14th January 2019, 15:09No clear values specified for R31 and C10.21 replies | 465 view(s)
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13th January 2019, 23:28FvM replied to a thread Spartan 6 - OSERDES2 to ODDR - Unroutable signals in PLD, SPLD, GAL, CPLD, FPGA DesignThe DDR output register is fed with half the final output data rate. This should allow to use general core registers for the 5:1 serializers. In...4 replies | 264 view(s)
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13th January 2019, 23:08That's an option. It's still rather difficult to interface the SMD transistor package to a heatsink. You can e.g. use massive thermal vias and mount...8 replies | 238 view(s)
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