FvM
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Yesterday, 18:16Many ideas, but what's the problem actually?9 replies | 126 view(s) -
Yesterday, 16:29dpaul replied to a thread Module 'xyz' does not have a timeunit/timeprecision specification in ... in PLD, SPLD, GAL, CPLD, FPGA Design1. Get a repo, SVN, Git -- best solution! 2. Get a filelist or .f file (tracking of files possible but not their contents). More details here -...5 replies | 115 view(s) -
Yesterday, 16:12FvM replied to a thread [SOLVED] Does Solid State Marx Generators actually work? in Analog Circuit DesignIf D3 never turns on, how is C6 other terminal jumping to 600V? There's no other current path provided. 1.7V specification is for 1A diode...19 replies | 447 view(s)
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Yesterday, 15:57You said Megohm range load, 200V supply, 50 mA current range. Which of the three specs should be corrected? E.g. 10 mA can be achieved with up to 20...9 replies | 126 view(s)
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Yesterday, 15:50None of both seem to be able to achieve correct DC bias with the given circuit, this might well explain the low AC gain. The bias condition for...4 replies | 78 view(s)
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Yesterday, 15:28Not sure what you are exactly asking? The capacitive region starts right of X=0 respectively Z=max and goes up to infinite frequency.2 replies | 51 view(s)
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Yesterday, 15:19FvM replied to a thread [SOLVED] Does Solid State Marx Generators actually work? in Analog Circuit DesignYes. Fig. 3 in the paper linked in post #4 is a simplified schematic. You should review the original paper for related questions and more elaborated...19 replies | 447 view(s)
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Yesterday, 11:44FvM replied to a thread Output <= registers(to_integer(address)) and intentional meta values in ASIC Design Methodologies and Tools (Digital)Means there's no synthesis advantage?9 replies | 208 view(s)
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Yesterday, 11:36FvM replied to a thread stretching the 0 pulse of a digital output with a certain T in Analog Integrated Circuit (IC) Design, Layout and FabricationI'm not sure what we are currently talking about because the original 100 ms delay shrunk to 100 ns in the meantime. There's a certain state of the...12 replies | 297 view(s)
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Yesterday, 11:20The usual mixing console pan circuit is using a single pot, as suggested by KlausST both series resistors connected to the same mono channel output....4 replies | 97 view(s)
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Yesterday, 10:31dpaul replied to a thread Module 'xyz' does not have a timeunit/timeprecision specification in ... in PLD, SPLD, GAL, CPLD, FPGA DesignI am seeing what you have written and it includes none of your project files. So I find it difficult to answer your question. What if you remove...5 replies | 115 view(s)
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Yesterday, 10:02I'm not aware of a liquid dielectric with sufficient high permittivity to serve your purpose. You can safely forget about this option.32 replies | 637 view(s)
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Yesterday, 09:51FvM replied to a thread Loop Compensation Characteristics with Degraded parts in Boost PFC. in Power ElectronicsEasy peasy has answered your question from a designers/instrument manufacturers perspective. To investigate the detail effects, perform a...4 replies | 78 view(s)
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Yesterday, 09:04You won't find an of-the-shelf CT allowing higher output swing than a few 10 or maximal 100 mV for 50 or 100 mA primary current with passive burden....14 replies | 224 view(s)
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Yesterday, 07:09FvM replied to a thread [SOLVED] Does Solid State Marx Generators actually work? in Analog Circuit DesignTo clarify the output point19 replies | 447 view(s)
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Yesterday, 06:58FvM replied to a thread SMPS selection for Big 6-Digit 7-SEGMENTS display as driver in MicrocontrollersThe word hasn't been used yet. But they discussed having anode and cathode drivers, just another word for multiplexed scheme.8 replies | 195 view(s)
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Yesterday, 06:56FvM replied to a thread Display lcd text from Fpga1 to Fpga2 via USB cable in PLD, SPLD, GAL, CPLD, FPGA DesignDid you already review the DE2 115 user manual? It describes USB host and device demonstrations.7 replies | 135 view(s)
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Yesterday, 06:35We can't discuss DC voltage levels without considering the OTA power supply. What are the input common mode and output voltage range? Presuming...4 replies | 78 view(s)
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18th June 2019, 22:39FvM replied to a thread [SOLVED] Does Solid State Marx Generators actually work? in Analog Circuit DesignI try to understand what your simulation has to do with the post #1 circuit. I believe that the latter doesn't work as expected, but what do you...19 replies | 447 view(s)
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18th June 2019, 19:06The datasheet gives many details. The CT is intended for 20 to 200 kHz frequency range. Primary inductance is relative low, thus you don't get...14 replies | 224 view(s)
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18th June 2019, 17:10Imagine a photo transistor as a high current gain transistor with a photo diode across CB junction. You can easily predict the observed behavior.2 replies | 94 view(s)
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18th June 2019, 17:06Sure, basically a similar phasor diagram as for series RLC, just flip voltage and current.4 replies | 104 view(s)
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18th June 2019, 17:03Brings up two questions: 1. Is 3300 ohm burden in the permitted range according to CT datasheet? 2. How does your multimeter measure voltage in the...14 replies | 224 view(s)
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18th June 2019, 16:15FvM replied to a thread Display lcd text from Fpga1 to Fpga2 via USB cable in PLD, SPLD, GAL, CPLD, FPGA DesignNext step would be to review the existing USB demonstration projects for this board (or boards with similar controller). If I remember right, most...7 replies | 135 view(s)
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18th June 2019, 15:27Sorry, my bad......didn't read #1 thoroughly.7 replies | 177 view(s)
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18th June 2019, 09:59Review the description of usual mixer consoles. There are one or multiple effect/monitor sums with separate send level control for each input...4 replies | 97 view(s)
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18th June 2019, 09:54The calculation in post #1 is wrong, you forgot the transformer turns ratio. With 1:100 ratio, the output voltage is only 1/100 of the calculated. As...14 replies | 224 view(s)
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18th June 2019, 09:48Taking the RLC series circuit as an example, all elements carry the same current, but voltages have different, even opposite phase according to the...4 replies | 104 view(s)
About FvM
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