Tab Content
More Activity
About dpaul

Basic Information

Areas of Interest
Area of specialization:
ASIC Design, PLD, SPLD, GAL, CPLD, FPGA Design, Microcontrollers
Optional Info
Location:
Germay
Interests:
Digital and Mixed-signal design
Occupation:
Engineer

Statistics


Total Posts
Total Posts
1,181
Posts Per Day
0.29
General Information
Last Activity
Today 14:48
Join Date
16th January 2008
Helpful Postings
Has Rated
42
Post Rated
Rated helpful 255 out of 255 times

9 Friends

  1. Anwesa Roy  Anwesa Roy is offline

    Member level 2

    Anwesa Roy
  2. DocIng  DocIng is offline

    Junior Member level 1

    DocIng
  3. fouwad  fouwad is offline

    Full Member level 4

    fouwad
  4. FvM  FvM is offline

    Super Moderator

    FvM
  5. guru2kiot  guru2kiot is offline

    Junior Member level 2

    guru2kiot
  6. hamidkavianathar  hamidkavianathar is offline

    Member level 4

    hamidkavianathar
  7. moh.haroun  moh.haroun is offline

    Full Member level 1

    moh.haroun
  8. shaiko  shaiko is offline

    Advanced Member level 5

    shaiko
  9. ujas  ujas is offline

    Newbie level 4

    ujas
Showing Friends 1 to 9 of 9
 

Experience


Points
Points
7,946
Level
21
Points: 7,946, Level: 21
 
Level up completed
Level up completed
28%
Points required
504

Activity


Activity
29.0%
Activity last 30 days
28.0%
Activity last 7 days
24.0%

Points


All Points for user
Points for User
2,596
Points for Reputation
518
Points for every day since registration
2,051
Points for Friends
27
All Points for threads
Points for threads
426
Points for Threads
52
Points for tagging threads
340
Points for replies
34
All Points for posts
Points for Posts
4,908
Points for Posts
3,561
Helpful Answers
1,275
Solved Threads
72
All Points for miscellaneous
Points for Misc
15
Points for article in vBulletin Blog
15

Activities


20th February 2019
03:05 dpaul has earned 1 Points for User points

19th February 2019
03:06 dpaul has earned 6 Points for Posts points
03:06 dpaul has earned 1 Points for threads points
03:06 dpaul has earned 1 Points for User points

16th February 2019
03:05 dpaul has earned 1 Points for User points

15th February 2019
03:06 dpaul has earned 1 Points for User points

12th February 2019
03:06 dpaul has earned 2 Points for User points

9th February 2019
03:06 dpaul has earned 5 Points for Posts points
03:06 dpaul has earned 2 Points for User points

8th February 2019
03:06 dpaul has earned 6 Points for Posts points
03:06 dpaul has earned 1 Points for User points

7th February 2019
03:05 dpaul has earned 3 Points for Posts points
03:05 dpaul has earned 1 Points for threads points

6th February 2019
03:05 dpaul has earned 1 Points for User points

5th February 2019
03:05 dpaul has earned 3 Points for Posts points
03:05 dpaul has earned 2 Points for threads points
03:05 dpaul has earned 1 Points for User points

2nd February 2019
03:05 dpaul has earned 1 Points for User points

31st January 2019
03:05 dpaul has earned 3 Points for User points

25th January 2019
03:05 dpaul has earned 1 Points for User points

Show Activities from all Users
View dpaul's Blog

Recent Entries

Using a Xilinx IP in your design without generating it using the Coregen flow.

by dpaul on 3rd July 2015 at 16:30
----------------------------------------------------------------------------------------------------
Using a Xilinx IP in your design without generating it using the Coregen flow.
----------------------------------------------------------------------------------------------------

I will take the example of the LogiCORE IP - AXI Interconnect v.1.06.a (DS768).

Consider the situation that you want to connect multiple masters and multiple slaves to a Xilinx

Read More

Categories
Uncategorized