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About dpaul

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Areas of Interest
Area of specialization:
ASIC Design, PLD, SPLD, GAL, CPLD, FPGA Design, Microcontrollers
Optional Info
Location:
Germany
Interests:
Digital design and test (ASIC & FPGA), Embeddd Systems
Occupation:
Engineer

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Recent Entries

Using a Xilinx IP in your design without generating it using the Coregen flow.

by dpaul on 3rd July 2015 at 16:30
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Using a Xilinx IP in your design without generating it using the Coregen flow.
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I will take the example of the LogiCORE IP - AXI Interconnect v.1.06.a (DS768).

Consider the situation that you want to connect multiple masters and multiple slaves to a Xilinx

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