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Re: LTspice...splitting LT1243 output into two separate pulse streams

the rising edge of the LT1243 clocks the DFF, s both transistors "switches" are on at the same time -
one turning on and one turning
wwfeldman Today, 16:31

Re: LTspice...splitting LT1243 output into two separate pulse streams

Thanks, this is purely sim and we wish to use the LT1243 as its so quik and eazy to use.

The attached (LTspice and schem) shows how it
treez Today, 16:02

Re: Power amplifier design (grounding)

Before all, have you ever considered Decoupling Capacitors placed juts after Lambda/4 Transmission Lines ?? You will have to place and be sure that they
BigBoss Today, 15:55

Re: The difference between IIP3 and P1dB

IP3 has theoretically 9.6dB more than P1dB and it shows Third Order Intermodulation only.It doesn't mean the the amplifier is more linear or less linear..
BigBoss Today, 15:47

Re: Solve Equations Verilog

in post 1, its a^7, in post its x^6 ?

the number of roots is equal to the highest exponent, so 7 roots and 6 roots, receptively
wwfeldman Today, 15:29

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