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C , VERILOG, VHDL.

C , VERILOG, VHDL.

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J
Hi Freinds,

exp level -- 4 to 10 plus
NP : immediate to 1 month
10 regs open -- we work in subcontract model also

we have openings are IP/SOC verification for Bangalore location
JD
Skill Set : SV/UVM and or Verilog/C/C++/Scripting knowledge in AXI/APB/PCIE/USB/Ethernet protocols... Read more…
Y
My group is having a project to be implemented on PUF(Physical unclonable functions) using Verilog. Having written the code in Verilog we are facing an error which we could not rectify even after several tries. It would be really helpful if you would help us rectify this error. And the error... Read more…
B
BM Yogini
procedural blocks like initial and always should be written inside module "module name".Try doing with this and update me if any error comes.

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