spacing between two devices/metals as per the technology

  1. layout
    when we have two different potentials in our circuit. Then in layout we put some spacing between those two devices/metals as per the technology
    can anyone please tell me the reason for that (i know one reason i.e, due to noise frequency cross talk may occur,other than this is there any reason)

  2. dick_freebird
    Regardless of potential there is a minimum spacing that can be
    reliably patterned by the lithography tools of the process flow.

    There may be additional reliability / defectivity related rules for
    high voltages when they demand more that the lithography

    Thin oxide reliability starts to worry around 7MV/cm. The
    deposited dielectrics, and the "seams" between layers,
    may withstand less.

    Technology docs ought to tell you whether there's any
    special voltage/distance concern.
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