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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: 26V Current Sense Amplifier

    Started by mmatheson, 3rd January 2018 01:50
    • Replies: 0
    • Views: 408
    3rd January 2018, 01:50 Go to last post
  2. Sticky Thread Sticky: Featured Reference Designs

    Started by mmatheson, 16th June 2016 22:04
    • Replies: 0
    • Views: 7,569
    16th June 2016, 22:04 Go to last post
  3. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 26,735
    3rd December 2007, 18:00 Go to last post
  1. Conductor via and dielectric via

    Started by Cyrina, Yesterday 14:13
    • Replies: 1
    • Views: 89
    Today, 00:39 Go to last post
  2. COLLECTOR region thickness in BJT

    Started by captain_haddock, Yesterday 20:15
    • Replies: 1
    • Views: 57
    Today, 00:34 Go to last post
  3. Plot of NMOS gate capacitance vs applied voltage ??

    Started by cmos_ajay, 22nd January 2018 13:50
    • Replies: 2
    • Views: 221
    22nd January 2018, 20:17 Go to last post
  4. width and length of cmos

    Started by Jasmine14, 21st January 2018 18:51
    • Replies: 4
    • Views: 199
    22nd January 2018, 19:48 Go to last post
  5. MOS switches / transmission gates

    Started by CAMALEAO, 30th August 2017 09:35
    • Replies: 5
    • Views: 760
    22nd January 2018, 17:18 Go to last post
  6. Substrate file and Layer map mismatch ADS

    Started by Cyrina, 22nd January 2018 10:02
    • Replies: 0
    • Views: 113
    22nd January 2018, 10:02 Go to last post
  7. Moved: Using an external clock for oscilloscope

    Started by venn_ng, 21st January 2018 23:32
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  8. Well Proximity Effect

    Started by NKSLP, 21st January 2018 06:16
    • Replies: 2
    • Views: 193
    21st January 2018, 20:02 Go to last post
  9. increase no'of multipliers vs VDD

    Started by circuitking, 20th January 2018 20:32
    • Replies: 6
    • Views: 266
    21st January 2018, 17:26 Go to last post
    • Replies: 16
    • Views: 1,149
    18th January 2018, 21:35 Go to last post
  10. Moved: How to get Transient simulation from this circuit and AC phae plot

    Started by Devi92, 16th January 2018 13:44
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    • Replies: 4
    • Views: 441
    14th January 2018, 17:09 Go to last post
  11. layout automatically generation

    Started by shanmei, 12th January 2018 17:35
    • Replies: 5
    • Views: 392
    14th January 2018, 02:38 Go to last post
  12. Problem using vpwlf with reference other than GND

    Started by sohaee, 10th January 2018 09:24
    • Replies: 8
    • Views: 402
    14th January 2018, 01:50 Go to last post
  13. source coudn't be read

    Started by Alipoursaadaty, 13th January 2018 16:06
    • Replies: 3
    • Views: 264
    13th January 2018, 19:04 Go to last post
  14. Moved: 5th Order Discrete Time Sigma Delta Modulator

    Started by Puppet123, 13th January 2018 15:53
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  15. 90nm calibre LVS error

    Started by Alipoursaadaty, 12th January 2018 09:26
    • Replies: 3
    • Views: 305
    13th January 2018, 17:17 Go to last post
  16. Dummy metal fill in virtuoso

    Started by sanjaysharmaiitk, 11th January 2018 14:52
    • Replies: 2
    • Views: 325
    12th January 2018, 18:48 Go to last post
  17. Moved: How to find input reflection coefficient in cadence

    Started by circuitking, 12th January 2018 12:50
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  18. Moved: flipped voltage follower details

    Started by simplsoft, 12th January 2018 09:44
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  19. Moved: voltage shiftier with conditional purpose

    Started by nimaz, 12th January 2018 09:53
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  20. Moved: Gate Design in Hspice software

    Started by nimaz, 12th January 2018 09:46
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  21. [SOLVED] 90nm calibre DRC error

    Started by Alipoursaadaty, 10th January 2018 21:41
    • Replies: 2
    • Views: 284
    11th January 2018, 05:02 Go to last post
    • Replies: 6
    • Views: 323
    10th January 2018, 16:08 Go to last post
    • Replies: 4
    • Views: 992
    10th January 2018, 07:20 Go to last post
  22. How to do QRC extraction

    Started by Bhanu_Pratap, 8th January 2018 15:03
    • Replies: 3
    • Views: 352
    9th January 2018, 01:25 Go to last post
  23. Mentor Calibredrv - how to create an "edge" in layout?

    Started by majd229, 8th January 2018 17:34
    • Replies: 0
    • Views: 285
    8th January 2018, 17:34 Go to last post
  24. Moved: Input matching without using resistors

    Started by circuitking, 8th January 2018 13:59
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  25. [SOLVED] Questions on complex layout design connections

    Started by Vijay Vinay, 3rd January 2018 18:29
    • Replies: 4
    • Views: 671
    4th January 2018, 14:35 Go to last post