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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] LIN transceivers that save board space & cost

    Started by B. David Miyares, 2nd April 2018 14:01
    • Replies: 0
    • Views: 252
    2nd April 2018, 14:01 Go to last post
  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 27,637
    3rd December 2007, 18:00 Go to last post
  1. MMWave Layout Issues in CMOS

    Started by Puppet123, Yesterday 02:30
    • Replies: 7
    • Views: 188
    Today, 17:14 Go to last post
  2. VCO gain and tuning range

    Started by posiba, Today 08:43
    • Replies: 2
    • Views: 67
    Today, 13:44 Go to last post
  3. Layer definition in TSMC 65nm

    Started by AllenD, 18th April 2018 04:49
    • Replies: 2
    • Views: 104
    Today, 10:35 Go to last post
    • Replies: 2
    • Views: 93
    Today, 08:59 Go to last post
  4. Common Centroid Capacitor Layout in Cadence

    Started by Puppet123, 17th April 2018 22:22
    • Replies: 2
    • Views: 102
    Yesterday, 23:12 Go to last post
    • Replies: 8
    • Views: 1,059
    Yesterday, 18:31 Go to last post
  5. Balanced OTA-C cascode IC design

    Started by sherif96, 23rd March 2018 15:03
    3 Pages
    1 2 3
    • Replies: 43
    • Views: 1,557
    Yesterday, 17:11 Go to last post
  6. Abutting transistors in TSMC65nm

    Started by Puppet123, 17th April 2018 22:35
    • Replies: 2
    • Views: 131
    18th April 2018, 20:04 Go to last post
    • Replies: 2
    • Views: 158
    18th April 2018, 18:55 Go to last post
    • Replies: 8
    • Views: 376
    18th April 2018, 08:03 Go to last post
    • Replies: 3
    • Views: 214
    17th April 2018, 22:28 Go to last post
  7. Long start-up time current reference

    Started by chandlerbing65nm, 17th April 2018 09:03
    • Replies: 2
    • Views: 105
    17th April 2018, 21:06 Go to last post
  8. offset voltage of opamp

    Started by chandlerbing65nm, 17th April 2018 16:33
    • Replies: 2
    • Views: 107
    17th April 2018, 20:57 Go to last post
  9. Current Reference SS problem

    Started by chandlerbing65nm, 15th April 2018 23:57
    • Replies: 1
    • Views: 155
    16th April 2018, 19:06 Go to last post
  10. Current Mirror Inaccuracy

    Started by chandlerbing65nm, 15th April 2018 19:58
    • Replies: 2
    • Views: 171
    15th April 2018, 21:22 Go to last post
  11. Transmission Gate Impedance Problem

    Started by andreneil15, 7th April 2018 05:47
    • Replies: 8
    • Views: 387
    15th April 2018, 03:18 Go to last post
  12. Common Centroid Layout

    Started by Puppet123, 12th April 2018 20:56
    • Replies: 5
    • Views: 311
    14th April 2018, 07:07 Go to last post
  13. Cadence Layout - Interdigitization

    Started by Puppet123, 13th April 2018 23:46
    • Replies: 1
    • Views: 199
    14th April 2018, 04:28 Go to last post
  14. characterizing semiconductors

    Started by Madbunny1, 12th April 2018 19:10
    • Replies: 2
    • Views: 168
    12th April 2018, 20:41 Go to last post
  15. Current mirror transistor connection

    Started by akbarza, 26th March 2018 12:56
    • Replies: 2
    • Views: 428
    12th April 2018, 15:09 Go to last post
    • Replies: 1
    • Views: 202
    12th April 2018, 15:04 Go to last post
    • Replies: 5
    • Views: 253
    11th April 2018, 17:48 Go to last post
  16. parameters of clock generators

    Started by chandlerbing65nm, 10th April 2018 18:41
    • Replies: 1
    • Views: 183
    10th April 2018, 21:25 Go to last post
  17. Hand calculation of PMOS OPA

    Started by chandlerbing65nm, 10th April 2018 04:10
    • Replies: 2
    • Views: 225
    10th April 2018, 18:36 Go to last post