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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 23,647
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 29,460
    21st March 2007, 21:21 Go to last post
    • Replies: 1
    • Views: 332
    Yesterday, 08:08 Go to last post
  1. Clock Divider from 921600Hz to 115200Hz

    Started by fatimamaz, 19th February 2018 12:35
    • Replies: 4
    • Views: 190
    19th February 2018, 21:16 Go to last post
  2. Tracking states of FSM (finite state machine) in Modelsim

    Started by mjuneja, 13th February 2018 10:57
    • Replies: 8
    • Views: 461
    16th February 2018, 17:59 Go to last post
    • Replies: 9
    • Views: 532
    16th February 2018, 04:02 Go to last post
    • Replies: 12
    • Views: 654
    14th February 2018, 09:44 Go to last post
  3. Send Binary Data Serially

    Started by fatimamaz, 12th February 2018 09:53
    • Replies: 3
    • Views: 266
    12th February 2018, 17:18 Go to last post
  4. accessing memory address in verilog

    Started by jasi, 12th February 2018 09:42
    • Replies: 5
    • Views: 272
    12th February 2018, 14:25 Go to last post
  5. Send Serial data through RS-232

    Started by fatimamaz, 29th January 2018 14:56
    • Replies: 5
    • Views: 638
    12th February 2018, 10:59 Go to last post
  6. Testbench for simple Register file

    Started by fadia, 11th February 2018 04:52
    • Replies: 0
    • Views: 306
    11th February 2018, 04:52 Go to last post
  7. Altera DE4 PCIe linux driver

    Started by promach, 8th February 2018 13:37
    • Replies: 4
    • Views: 309
    9th February 2018, 17:21 Go to last post
  8. Idelayctrl, idelay, odelay....

    Started by velu.plg, 9th February 2018 10:54
    • Replies: 1
    • Views: 208
    9th February 2018, 12:58 Go to last post
  9. Questions on Asynchronous FIFO

    Started by promach, 30th January 2018 03:44
    • Replies: 8
    • Views: 526
    9th February 2018, 05:51 Go to last post
    • Replies: 6
    • Views: 377
    9th February 2018, 02:52 Go to last post
    • Replies: 11
    • Views: 747
    8th February 2018, 22:52 Go to last post
    • Replies: 1
    • Views: 294
    8th February 2018, 08:42 Go to last post
  10. How to reduce the Data Delay time constraint?

    Started by Hugo17, 8th February 2018 08:28
    • Replies: 0
    • Views: 249
    8th February 2018, 08:28 Go to last post
  11. Digital circuit to divide larger bits into smaller bits

    Started by mthakur, 30th January 2018 07:34
    • Replies: 12
    • Views: 890
    8th February 2018, 04:21 Go to last post
  12. [SOLVED] How I/Os are realized inside FPGA

    Started by mjuneja, 3rd February 2018 17:22
    • Replies: 10
    • Views: 768
    7th February 2018, 17:28 Go to last post
  13. verilog-problem write text file

    Started by jalal.baba, 7th February 2018 10:59
    • Replies: 1
    • Views: 290
    7th February 2018, 13:25 Go to last post
  14. Conversion of octal to decimal

    Started by sugubai, 31st January 2018 18:44
    • Replies: 13
    • Views: 817
    6th February 2018, 00:00 Go to last post
  15. verilog-problem read decimal value in text file

    Started by jalal.baba, 5th February 2018 17:04
    • Replies: 3
    • Views: 368
    5th February 2018, 23:05 Go to last post
  16. Vivado error please help with library

    Started by abimann, 5th February 2018 15:56
    • Replies: 1
    • Views: 297
    5th February 2018, 17:08 Go to last post
  17. Clock generator in psoc by using verilog

    Started by jasi, 23rd January 2018 10:29
    • Replies: 6
    • Views: 644
    4th February 2018, 18:52 Go to last post
  18. Help in simulating ALU with register file

    Started by fadia, 4th February 2018 00:55
    • Replies: 0
    • Views: 321
    4th February 2018, 00:55 Go to last post
  19. is nested for loop supported in verilog

    Started by tayyab786, 3rd February 2018 19:36
    • Replies: 1
    • Views: 324
    3rd February 2018, 20:37 Go to last post
  20. Unconstrained FPGA ADC-Outputs

    Started by Hugo17, 2nd February 2018 10:40
    • Replies: 3
    • Views: 429
    2nd February 2018, 16:14 Go to last post
    • Replies: 0
    • Views: 291
    2nd February 2018, 08:28 Go to last post
    • Replies: 3
    • Views: 385
    1st February 2018, 11:41 Go to last post