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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 23,266
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 29,067
    21st March 2007, 21:21 Go to last post
  1. CY7C68013A labview interface

    Started by jackobian, 12th January 2018 11:04
    • Replies: 1
    • Views: 241
    Today, 16:55 Go to last post
  2. [old software] XC3000/A Software

    Started by DeepTHought, Today 16:45
    • Replies: 0
    • Views: 58
    Today, 16:45 Go to last post
    • Replies: 1
    • Views: 204
    Yesterday, 15:38 Go to last post
  3. non responsive vhdl code in FPGA board

    Started by ananthan95, 29th December 2017 06:58
    • Replies: 10
    • Views: 727
    Yesterday, 09:13 Go to last post
  4. Integer convert to std_logic_vector ?

    Started by abimann, 30th December 2017 17:33
    • Replies: 3
    • Views: 429
    Yesterday, 08:48 Go to last post
  5. Error in verilog code for stopwatch

    Started by Nyom, 18th January 2018 22:59
    • Replies: 6
    • Views: 231
    Yesterday, 01:30 Go to last post
    • Replies: 5
    • Views: 383
    18th January 2018, 14:19 Go to last post
    • Replies: 4
    • Views: 402
    18th January 2018, 10:52 Go to last post
  6. TIBPAL22vp10 compiler

    Started by wjr1955, 17th January 2018 21:28
    • Replies: 1
    • Views: 149
    18th January 2018, 10:05 Go to last post
  7. How to receive PWM and edit it ?

    Started by abimann, 30th December 2017 17:39
    • Replies: 13
    • Views: 894
    16th January 2018, 08:08 Go to last post
  8. Conversion from std_logic_vector to sfixed

    Started by Hugo17, 15th January 2018 08:31
    • Replies: 2
    • Views: 204
    16th January 2018, 07:06 Go to last post
  9. Wait on clocking block input signals

    Started by amvrao, 12th January 2018 12:48
    • Replies: 2
    • Views: 355
    15th January 2018, 15:59 Go to last post
    • Replies: 4
    • Views: 367
    15th January 2018, 09:27 Go to last post
    • Replies: 4
    • Views: 234
    12th January 2018, 14:32 Go to last post
    • Replies: 4
    • Views: 282
    12th January 2018, 07:29 Go to last post
    • Replies: 4
    • Views: 421
    10th January 2018, 20:30 Go to last post
    • Replies: 0
    • Views: 184
    10th January 2018, 14:20 Go to last post
    • Replies: 7
    • Views: 396
    10th January 2018, 12:35 Go to last post
  10. [SOLVED] irrational clk period

    Started by nsgil85, 31st December 2017 08:59
    2 Pages
    1 2
    • Replies: 26
    • Views: 1,153
    8th January 2018, 17:00 Go to last post
  11. QPSK Modulator Design Issues

    Started by NichollsGlen, 28th December 2017 03:39
    • Replies: 2
    • Views: 453
    8th January 2018, 02:44 Go to last post
  12. [Altera] altera_mf lib -> how to compile/map?

    Started by ivlsi, 7th January 2018 02:53
    • Replies: 0
    • Views: 283
    7th January 2018, 02:53 Go to last post
  13. What is the Total Negative Slack

    Started by Serwan Bamerni, 6th January 2018 00:27
    • Replies: 4
    • Views: 417
    6th January 2018, 16:17 Go to last post
  14. How to get real time instances of an ecg signal

    Started by josephine1234, 5th January 2018 13:39
    • Replies: 4
    • Views: 350
    5th January 2018, 15:18 Go to last post
  15. Advice on configuring vim & syntastic for vhdl

    Started by wesleytaylor, 5th January 2018 10:23
    • Replies: 0
    • Views: 261
    5th January 2018, 10:23 Go to last post
    • Replies: 5
    • Views: 419
    4th January 2018, 09:17 Go to last post
    • Replies: 1
    • Views: 297
    3rd January 2018, 18:37 Go to last post