1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    105,918
Page 1 of 740 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 22199

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 24,313
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 30,118
    21st March 2007, 21:21 Go to last post
  1. VHDL state machine execution

    Started by hareeshP, Yesterday 12:15
    • Replies: 2
    • Views: 73
    Yesterday, 19:17 Go to last post
  2. synplify identify instrumentor......

    Started by velu.plg, Yesterday 09:57
    • Replies: 1
    • Views: 69
    Yesterday, 16:19 Go to last post
  3. [SOLVED] Glitch Filter VHDL // Lattice document

    Started by player80, 20th April 2018 14:43
    • Replies: 6
    • Views: 190
    20th April 2018, 20:08 Go to last post
  4. testbench without a DUT

    Started by paulr127, 19th April 2018 22:20
    • Replies: 7
    • Views: 198
    20th April 2018, 17:24 Go to last post
  5. Help with this FPGA xilinx spartan xc3s50

    Started by FGDGDFGG, 18th April 2018 10:46
    • Replies: 5
    • Views: 292
    20th April 2018, 15:41 Go to last post
    • Replies: 5
    • Views: 160
    20th April 2018, 09:39 Go to last post
  6. [SOLVED] How do I read a test bench input from a txt file?

    Started by ggiacomo, 17th April 2018 09:55
    • Replies: 6
    • Views: 199
    19th April 2018, 18:39 Go to last post
  7. best method for control memory in fpga

    Started by jalal.baba, 17th April 2018 19:51
    • Replies: 5
    • Views: 222
    19th April 2018, 08:55 Go to last post
  8. altera fpga update from remote

    Started by franticEB, 18th April 2018 17:45
    • Replies: 1
    • Views: 131
    18th April 2018, 22:28 Go to last post
    • Replies: 0
    • Views: 83
    18th April 2018, 14:19 Go to last post
    • Replies: 7
    • Views: 420
    15th April 2018, 07:42 Go to last post
  9. Cannot continue(fatal error) problems with lifo

    Started by chenobi, 13th April 2018 12:11
    • Replies: 8
    • Views: 317
    13th April 2018, 17:46 Go to last post
    • Replies: 6
    • Views: 469
    13th April 2018, 12:40 Go to last post
  10. if statement within a generate for loop

    Started by jasmine123, 12th April 2018 07:47
    • Replies: 7
    • Views: 308
    13th April 2018, 03:19 Go to last post
  11. setup violation in physical designing

    Started by vinu114, 12th April 2018 07:05
    • Replies: 3
    • Views: 223
    13th April 2018, 01:44 Go to last post
    • Replies: 8
    • Views: 615
    12th April 2018, 10:00 Go to last post
  12. Timing constraints for clock domain crossing

    Started by urbanzrim, 10th April 2018 07:31
    • Replies: 6
    • Views: 380
    12th April 2018, 05:45 Go to last post
  13. Is logic cell a technology independent parameter

    Started by rafimiet, 11th April 2018 09:58
    • Replies: 7
    • Views: 337
    12th April 2018, 04:51 Go to last post
  14. Simulating Xilinx smpte sdi core

    Started by paulr127, 10th April 2018 12:04
    • Replies: 8
    • Views: 401
    11th April 2018, 15:12 Go to last post
  15. Kintex Transceiver bank configuration

    Started by beginner_EDA, 11th April 2018 13:39
    • Replies: 0
    • Views: 194
    11th April 2018, 13:39 Go to last post
  16. Output pixel larger than the desired pixel

    Started by fatimamaz, 27th March 2018 13:04
    • Replies: 3
    • Views: 479
    10th April 2018, 10:21 Go to last post
  17. [SOLVED] Verilog error , Pls help

    Started by abimann, 16th March 2018 16:31
    • Replies: 13
    • Views: 1,165
    10th April 2018, 02:29 Go to last post
  18. Assignment of DSP Slices in FPGA

    Started by expertengr, 6th April 2018 10:07
    • Replies: 5
    • Views: 394
    9th April 2018, 18:47 Go to last post
    • Replies: 3
    • Views: 270
    9th April 2018, 14:24 Go to last post
  19. RF/IF signal recorder board

    Started by ali_th, 9th April 2018 05:04
    • Replies: 2
    • Views: 229
    9th April 2018, 12:08 Go to last post
  20. hd-sdi interface testing

    Started by paulr127, 6th April 2018 13:41
    • Replies: 9
    • Views: 555
    8th April 2018, 11:53 Go to last post
  21. Techniques to solve metastability issue in VHDL

    Started by expertengr, 6th April 2018 10:17
    • Replies: 14
    • Views: 600
    7th April 2018, 06:59 Go to last post
    • Replies: 0
    • Views: 214
    6th April 2018, 12:06 Go to last post