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Threads 1 to 30 of 22194

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 24,285
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 30,088
    21st March 2007, 21:21 Go to last post
  1. best method for control memory in fpga

    Started by jalal.baba, 17th April 2018 19:51
    • Replies: 5
    • Views: 151
    Today, 08:55 Go to last post
  2. altera fpga update from remote

    Started by franticEB, Yesterday 17:45
    • Replies: 1
    • Views: 89
    Yesterday, 22:28 Go to last post
  3. Help with this FPGA xilinx spartan xc3s50

    Started by FGDGDFGG, Yesterday 10:46
    • Replies: 3
    • Views: 136
    Yesterday, 15:00 Go to last post
    • Replies: 0
    • Views: 54
    Yesterday, 14:19 Go to last post
  4. [SOLVED] How do I read a test bench input from a txt file?

    Started by ggiacomo, 17th April 2018 09:55
    • Replies: 4
    • Views: 113
    17th April 2018, 12:11 Go to last post
    • Replies: 7
    • Views: 372
    15th April 2018, 07:42 Go to last post
  5. Cannot continue(fatal error) problems with lifo

    Started by chenobi, 13th April 2018 12:11
    • Replies: 8
    • Views: 281
    13th April 2018, 17:46 Go to last post
    • Replies: 6
    • Views: 440
    13th April 2018, 12:40 Go to last post
  6. if statement within a generate for loop

    Started by jasmine123, 12th April 2018 07:47
    • Replies: 7
    • Views: 269
    13th April 2018, 03:19 Go to last post
  7. setup violation in physical designing

    Started by vinu114, 12th April 2018 07:05
    • Replies: 3
    • Views: 196
    13th April 2018, 01:44 Go to last post
    • Replies: 8
    • Views: 575
    12th April 2018, 10:00 Go to last post
  8. Timing constraints for clock domain crossing

    Started by urbanzrim, 10th April 2018 07:31
    • Replies: 6
    • Views: 340
    12th April 2018, 05:45 Go to last post
  9. Is logic cell a technology independent parameter

    Started by rafimiet, 11th April 2018 09:58
    • Replies: 7
    • Views: 299
    12th April 2018, 04:51 Go to last post
  10. Simulating Xilinx smpte sdi core

    Started by paulr127, 10th April 2018 12:04
    • Replies: 8
    • Views: 358
    11th April 2018, 15:12 Go to last post
  11. Kintex Transceiver bank configuration

    Started by beginner_EDA, 11th April 2018 13:39
    • Replies: 0
    • Views: 171
    11th April 2018, 13:39 Go to last post
  12. Output pixel larger than the desired pixel

    Started by fatimamaz, 27th March 2018 13:04
    • Replies: 3
    • Views: 451
    10th April 2018, 10:21 Go to last post
  13. [SOLVED] Verilog error , Pls help

    Started by abimann, 16th March 2018 16:31
    • Replies: 13
    • Views: 1,121
    10th April 2018, 02:29 Go to last post
  14. Assignment of DSP Slices in FPGA

    Started by expertengr, 6th April 2018 10:07
    • Replies: 5
    • Views: 364
    9th April 2018, 18:47 Go to last post
    • Replies: 3
    • Views: 243
    9th April 2018, 14:24 Go to last post
  15. RF/IF signal recorder board

    Started by ali_th, 9th April 2018 05:04
    • Replies: 2
    • Views: 201
    9th April 2018, 12:08 Go to last post
  16. hd-sdi interface testing

    Started by paulr127, 6th April 2018 13:41
    • Replies: 9
    • Views: 515
    8th April 2018, 11:53 Go to last post
  17. Techniques to solve metastability issue in VHDL

    Started by expertengr, 6th April 2018 10:17
    • Replies: 14
    • Views: 554
    7th April 2018, 06:59 Go to last post
    • Replies: 0
    • Views: 192
    6th April 2018, 12:06 Go to last post
  18. Need logic that implement in Verilog coding

    Started by tayyab786, 6th April 2018 08:32
    • Replies: 0
    • Views: 206
    6th April 2018, 08:32 Go to last post
  19. declaring a constant value for all modules in verilog

    Started by dipin, 6th April 2018 06:12
    • Replies: 3
    • Views: 233
    6th April 2018, 07:39 Go to last post
  20. Usage of HP and HR IO banks and their selection

    Started by Alauddin123, 5th April 2018 06:54
    • Replies: 1
    • Views: 303
    5th April 2018, 07:29 Go to last post
  21. 12 Hour Clock using VHDL

    Started by triplel06, 3rd April 2018 01:12
    • Replies: 8
    • Views: 598
    4th April 2018, 16:59 Go to last post
  22. [MOVED] Need Verilog code for Ethernet protocol

    Started by mhafdhia, 4th April 2018 01:30
    • Replies: 2
    • Views: 376
    4th April 2018, 08:52 Go to last post