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Threads 22021 to 22050 of 22197

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Designing of a 16 state convolutional Decoder

    Started by Aircraft Maniac, 5th June 2003 07:29
    • Replies: 0
    • Views: 1,340
    5th June 2003, 07:29 Go to last post
  2. Closed: Who has the sch of Altera Byteblaster II ?

    Started by cd505, 4th June 2003 02:25
    • Replies: 2
    • Views: 2,027
    4th June 2003, 20:00 Go to last post
  3. Closed: Can *C9572 Design Tri state

    Started by J_expoler2, 1st June 2003 03:50
    • Replies: 2
    • Views: 1,359
    2nd June 2003, 10:59 Go to last post
  4. Closed: how i design LIFO on FPGA

    Started by J_expoler2, 23rd May 2003 09:32
    • Replies: 3
    • Views: 2,221
    2nd June 2003, 02:49 Go to last post
  5. Closed: Looking for resources on 64b/65b encoding

    Started by it_boy, 30th May 2003 17:33
    • Replies: 0
    • Views: 2,219
    30th May 2003, 17:33 Go to last post
  6. Closed: Programmer for PA7540P ??

    Started by Myself, 30th May 2003 15:29
    • Replies: 0
    • Views: 1,233
    30th May 2003, 15:29 Go to last post
  7. Closed: How to use single macrocell in CPLD of xilinx?

    Started by cfxok, 27th May 2003 16:41
    • Replies: 2
    • Views: 1,636
    29th May 2003, 07:01 Go to last post
  8. Closed: iMPACT gives me xc9572_unsupported

    Started by kras, 7th May 2003 15:26
    • Replies: 5
    • Views: 2,326
    28th May 2003, 13:04 Go to last post
  9. Closed: IEEE.std_logic_misc.ALL

    Started by mcfly, 28th May 2003 04:48
    • Replies: 2
    • Views: 4,011
    28th May 2003, 10:36 Go to last post
  10. Closed: the clock of Xilinx Vetex2 FPGA?

    Started by lvwx, 26th May 2003 14:52
    • Replies: 2
    • Views: 1,677
    27th May 2003, 02:48 Go to last post
  11. Closed: Timing simulation of two FPGA

    Started by irum4, 26th May 2003 14:33
    • Replies: 0
    • Views: 1,224
    26th May 2003, 14:33 Go to last post
  12. Closed: JHDL - link and recommendation

    Started by Ohh, 26th May 2003 10:09
    • Replies: 0
    • Views: 1,378
    26th May 2003, 10:09 Go to last post
  13. Closed: PCM-to-NRZ, NRZ-to-PCM - how?

    Started by Laplace, 25th May 2003 01:42
    • Replies: 1
    • Views: 1,617
    25th May 2003, 08:40 Go to last post
  14. Closed: Using internal oscilator on an FPGA

    Started by happytronic, 24th May 2003 17:13
    • Replies: 2
    • Views: 2,124
    24th May 2003, 17:33 Go to last post
  15. Closed: Schmitt input for xilinx's spartan2 design.

    Started by zcq, 24th April 2003 04:06
    • Replies: 8
    • Views: 2,894
    24th May 2003, 16:25 Go to last post
  16. Closed: How to calculate FPGA MIPS ?

    Started by Bartart, 22nd May 2003 12:20
    • Replies: 1
    • Views: 3,052
    23rd May 2003, 19:04 Go to last post
  17. Closed: help me for CPLD power reduction tech??

    Started by niks, 23rd May 2003 10:14
    • Replies: 2
    • Views: 1,337
    23rd May 2003, 18:50 Go to last post
  18. Closed: xnf file implementation - help needed

    Started by it_boy, 28th April 2003 06:12
    • Replies: 2
    • Views: 1,542
    22nd May 2003, 09:43 Go to last post
  19. Closed: Modelsim 5.5f and Windows XP

    Started by eltonjohn, 20th May 2003 17:19
    • Replies: 1
    • Views: 1,935
    21st May 2003, 06:42 Go to last post
  20. Closed: REQ: METHODLOGIES ON COPYING CPLD

    Started by humbleson, 18th May 2003 04:34
    • Replies: 1
    • Views: 1,595
    21st May 2003, 06:35 Go to last post
  21. Closed: a problem about configuration for xilinx FPGA using a CPLD

    Started by deebar, 8th April 2003 08:53
    • Replies: 2
    • Views: 2,294
    20th May 2003, 16:41 Go to last post
  22. [SOLVED] usb2.0 UTMI model - share please

    Started by smarty, 20th May 2003 15:22
    • Replies: 0
    • Views: 1,621
    20th May 2003, 15:22 Go to last post
  23. Closed: AHDL language help !!!!!

    Started by Rfboy, 8th May 2003 14:44
    • Replies: 4
    • Views: 2,036
    20th May 2003, 07:20 Go to last post
  24. Closed: MP3 player to target an FPGA

    Started by happytronic, 16th May 2003 01:50
    • Replies: 2
    • Views: 2,340
    16th May 2003, 17:59 Go to last post
  25. Closed: Problem programming XC95108

    Started by kras, 14th May 2003 08:11
    • Replies: 3
    • Views: 2,219
    15th May 2003, 07:34 Go to last post
  26. Closed: How can I programme single gates in structure of CPLD orFPGA

    Started by smiga, 14th May 2003 10:39
    • Replies: 0
    • Views: 1,604
    14th May 2003, 10:39 Go to last post
  27. Closed: Any one have s0urcec*de 74LS193 on veri10g

    Started by J_expoler2, 14th May 2003 04:34
    • Replies: 0
    • Views: 1,287
    14th May 2003, 04:34 Go to last post
  28. Closed: Any suggestions on how to fine-tune the FPGA implementation

    Started by jasonxie, 8th May 2003 00:09
    • Replies: 5
    • Views: 1,701
    13th May 2003, 19:33 Go to last post
  29. Closed: SystemView and Xilinx CoreGen

    Started by twinsen, 13th May 2003 08:38
    • Replies: 0
    • Views: 1,847
    13th May 2003, 08:38 Go to last post
  30. Closed: Fraction-N frequency divider

    Started by bjwljh, 12th May 2003 01:34
    • Replies: 1
    • Views: 2,784
    12th May 2003, 07:14 Go to last post