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Threads 1501 to 1530 of 22197

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: How to handle Xilinx virtex5 Vccint?

    Started by u24c02, 14th May 2016 03:40
    • Replies: 5
    • Views: 508
    17th May 2016, 00:27 Go to last post
  2. Closed: Xilinx blockset missing in simulink library

    Started by pouram, 16th May 2016 07:48
    • Replies: 1
    • Views: 525
    16th May 2016, 19:15 Go to last post
  3. Closed: Any software to visualize the synthesized hardware

    Started by garvind25, 16th May 2016 16:16
    • Replies: 4
    • Views: 391
    16th May 2016, 17:42 Go to last post
  4. Closed: Sorting the bits of a 32-bit vector.

    Started by alexmihai, 14th May 2016 20:22
    • Replies: 5
    • Views: 537
    16th May 2016, 10:35 Go to last post
  5. [SOLVED]Closed: Problem with black box in Matlab System generator

    Started by Serwan Bamerni, 14th May 2016 03:24
    • Replies: 2
    • Views: 519
    14th May 2016, 19:43 Go to last post
  6. Closed: black box implemenation from system generator matlab

    Started by prashanthi999, 19th November 2015 06:01
    • Replies: 4
    • Views: 777
    14th May 2016, 03:27 Go to last post
  7. Closed: De0-Nano Accelerometer

    Started by YS31, 13th May 2016 19:55
    • Replies: 0
    • Views: 554
    13th May 2016, 19:55 Go to last post
  8. Closed: NgdBuild:604 problem

    Started by Ananhasaasneh77, 12th May 2016 16:24
    • Replies: 9
    • Views: 985
    13th May 2016, 17:07 Go to last post
  9. Closed: NCO IP tool altera vhdl(phi_inc_i)

    Started by Kosyas41, 12th May 2016 12:47
    • Replies: 7
    • Views: 780
    13th May 2016, 16:52 Go to last post
  10. Closed: uart with sd controller

    Started by Ananhasaasneh77, 13th May 2016 12:46
    • Replies: 7
    • Views: 567
    13th May 2016, 16:50 Go to last post
  11. Closed: Verilog error: near text "wire" expecting a direction

    Started by nizdom, 12th May 2016 09:51
    • Replies: 2
    • Views: 1,780
    12th May 2016, 14:19 Go to last post
  12. Closed: Difference between stream signals in PCIE and in AXI DMA

    Started by biju4u90, 12th May 2016 07:45
    • Replies: 0
    • Views: 483
    12th May 2016, 07:45 Go to last post
  13. Closed: Xilinx Series 7 Memory Controller - "app_wdf_rdy" signal

    Started by shaiko, 12th April 2016 19:53
    • Replies: 11
    • Views: 1,126
    12th May 2016, 03:00 Go to last post
  14. Closed: how to design 32 bit barrel shifter

    Started by sunilraj.papu, 8th May 2016 11:45
    • Replies: 5
    • Views: 892
    11th May 2016, 17:28 Go to last post
  15. Closed: scaling factor. 2^n or (2^n - 1)

    Started by bravoegg, 10th May 2016 14:48
    • Replies: 9
    • Views: 689
    11th May 2016, 16:10 Go to last post
  16. [SOLVED]Closed: VGA controller for spartan 3

    Started by Basu_Gouda, 30th April 2016 05:57
    • Replies: 6
    • Views: 926
    11th May 2016, 15:53 Go to last post
  17. Closed: Xilinx Power Analysis of BRAM with XPE

    Started by wesleytaylor, 11th May 2016 09:12
    • Replies: 1
    • Views: 426
    11th May 2016, 14:21 Go to last post
  18. Closed: Show Grayscale Image in Verilog in DE1

    Started by nizdom, 10th May 2016 07:25
    • Replies: 2
    • Views: 665
    11th May 2016, 06:20 Go to last post
    • Replies: 5
    • Views: 992
    10th May 2016, 21:36 Go to last post
  19. [SOLVED]Closed: .mem file reading byte by byte in tcl

    Started by telangamey_ei, 3rd May 2016 15:33
    • Replies: 8
    • Views: 876
    10th May 2016, 09:44 Go to last post
  20. Closed: design of pid controller in vrilog

    Started by pamasapr, 10th May 2016 08:58
    • Replies: 1
    • Views: 385
    10th May 2016, 09:06 Go to last post
  21. Closed: Suggestions for FPGA kits

    Started by MSAKARIM, 8th May 2016 12:09
    • Replies: 5
    • Views: 580
    10th May 2016, 08:44 Go to last post
  22. Closed: spartan 3e interface with laptop

    Started by harismurtaza, 9th May 2016 08:56
    • Replies: 2
    • Views: 459
    9th May 2016, 16:57 Go to last post
  23. Closed: delay between consecutive pulses.....

    Started by aditiv, 8th May 2016 18:35
    • Replies: 1
    • Views: 366
    8th May 2016, 21:46 Go to last post
  24. Closed: transfer data from spi master to spi slave.

    Started by Ananhasaasneh77, 6th May 2016 16:33
    2 Pages
    1 2
    • Replies: 24
    • Views: 1,700
    8th May 2016, 16:08 Go to last post
  25. Closed: vhdl 2 dimensional array range

    Started by rourabpaul, 7th May 2016 10:40
    • Replies: 5
    • Views: 836
    8th May 2016, 07:40 Go to last post
  26. Closed: FMC HPC1 and HPC2 in virtex 7 vc707 board usage ???

    Started by anilineda, 6th May 2016 11:31
    • Replies: 1
    • Views: 411
    6th May 2016, 17:47 Go to last post
  27. UCF for spi in nexys3

    Started by Ananhasaasneh77, 2nd May 2016 15:00
    3 Pages
    1 2 3
    • Replies: 43
    • Views: 2,449
    6th May 2016, 16:41 Go to last post
  28. [SOLVED]Closed: Active high and active low signals

    Started by Kosyas41, 6th May 2016 14:00
    • Replies: 1
    • Views: 442
    6th May 2016, 15:18 Go to last post