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Threads 1501 to 1530 of 22052

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: 10-Bit Counter in Altera DE1 using Verilog

    Started by nizdom, 13th March 2016 13:42
    • Replies: 6
    • Views: 1,155
    15th March 2016, 12:35 Go to last post
  2. Closed: Process in VHDL code

    Started by MSAKARIM, 14th March 2016 17:22
    • Replies: 7
    • Views: 659
    15th March 2016, 10:38 Go to last post
  3. Closed: How to test the fpga base array?

    Started by bjzhangwn, 14th March 2016 16:23
    • Replies: 2
    • Views: 509
    15th March 2016, 09:16 Go to last post
  4. Closed: Verilog assign &

    Started by shaiko, 14th March 2016 09:17
    • Replies: 6
    • Views: 559
    14th March 2016, 22:05 Go to last post
  5. Closed: how to give a variable array in vhdl for papilio one

    Started by fisat, 14th March 2016 09:41
    • Replies: 1
    • Views: 415
    14th March 2016, 10:40 Go to last post
  6. Closed: Choosing between matlab and simulink

    Started by Sunayana Chakradhar, 11th March 2016 16:49
    • Replies: 4
    • Views: 539
    12th March 2016, 13:36 Go to last post
  7. Closed: Designing a packet processor on the FPGA ZC7020

    Started by Sunayana Chakradhar, 11th March 2016 17:02
    • Replies: 3
    • Views: 458
    12th March 2016, 08:24 Go to last post
  8. Closed: Using generics in VHDL modules

    Started by Binome, 10th March 2016 11:44
    • Replies: 5
    • Views: 574
    12th March 2016, 03:45 Go to last post
  9. Closed: 4 bit up down counter with programmable modulo value

    Started by amd1416, 9th March 2016 16:15
    • Replies: 18
    • Views: 1,600
    11th March 2016, 18:58 Go to last post
  10. Closed: An strange error message : ERROR:Anno:169

    Started by msdarvishi, 10th March 2016 18:43
    • Replies: 2
    • Views: 502
    10th March 2016, 23:30 Go to last post
  11. Closed: Multi-core simulation in Modelsim

    Started by ustinoff, 8th March 2016 20:08
    • Replies: 13
    • Views: 1,850
    10th March 2016, 08:15 Go to last post
  12. Closed: DDR DATA Sampling method

    Started by nsgil85, 8th March 2016 09:06
    • Replies: 3
    • Views: 466
    8th March 2016, 10:39 Go to last post
  13. Closed: Car Parking using Verilog

    Started by nizdom, 7th March 2016 15:23
    • Replies: 3
    • Views: 1,385
    8th March 2016, 09:22 Go to last post
  14. [SOLVED]Closed: When do we call that 2 clocks are not synchronized?

    Started by VuTang, 3rd March 2016 10:22
    • Replies: 9
    • Views: 714
    7th March 2016, 07:06 Go to last post
  15. Closed: VHDL noobie 4 by 4 Sequential multiplier help

    Started by DosPesos, 6th March 2016 03:29
    • Replies: 2
    • Views: 684
    6th March 2016, 21:33 Go to last post
  16. [SOLVED]Closed: even parity check with data flow operators

    Started by mohsansaleem, 5th March 2016 13:26
    • Replies: 5
    • Views: 514
    5th March 2016, 17:53 Go to last post
  17. Closed: Audio Processor Using FPGA

    Started by mlpin94, 5th March 2016 07:46
    • Replies: 1
    • Views: 552
    5th March 2016, 10:38 Go to last post
  18. Closed: Lattice ICE40 programming

    Started by am85, 4th March 2016 21:22
    • Replies: 0
    • Views: 910
    4th March 2016, 21:22 Go to last post
  19. Closed: FPGA configuration memory device alternatives

    Started by matrixofdynamism, 3rd March 2016 15:48
    • Replies: 11
    • Views: 849
    4th March 2016, 16:27 Go to last post
  20. Closed: ADMA on SD Host Controller

    Started by ismailov-e, 29th February 2016 05:24
    • Replies: 1
    • Views: 581
    4th March 2016, 07:53 Go to last post
  21. Closed: How to setup the control interface for the Avalon-MM?

    Started by Hugo17, 3rd March 2016 14:36
    • Replies: 0
    • Views: 529
    3rd March 2016, 14:36 Go to last post
  22. Closed: What is meant by straddled TLP in PCIE?

    Started by biju4u90, 3rd March 2016 07:12
    • Replies: 0
    • Views: 442
    3rd March 2016, 07:12 Go to last post
  23. Closed: atan LUT vhdl from 1/8 quarter to full circle

    Started by jackobian, 29th February 2016 06:07
    • Replies: 6
    • Views: 843
    1st March 2016, 23:23 Go to last post
  24. Closed: Xilinx Aurora protocol efficiency

    Started by shaiko, 29th February 2016 10:16
    • Replies: 8
    • Views: 1,028
    1st March 2016, 15:33 Go to last post
  25. [SOLVED]Closed: simulation strange behaviour of clock signals

    Started by LatticeSemiconductor, 1st March 2016 12:45
    • Replies: 3
    • Views: 405
    1st March 2016, 14:02 Go to last post
  26. Closed: ADC0804 and FPGA interface

    Started by enit268, 1st March 2016 13:02
    • Replies: 1
    • Views: 513
    1st March 2016, 13:40 Go to last post
  27. Closed: rtl integration documents

    Started by sun_ray, 26th February 2016 13:07
    2 Pages
    1 2
    • Replies: 24
    • Views: 1,706
    1st March 2016, 12:02 Go to last post