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Threads 15001 to 15030 of 22052

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: random number generator

    Started by ruwanika, 14th May 2008 05:25
    • Replies: 1
    • Views: 1,176
    14th May 2008, 07:47 Go to last post
  2. Closed: assign statement (Blocking & Non Blocking)

    Started by kungfu007, 12th May 2008 17:36
    • Replies: 2
    • Views: 1,793
    13th May 2008, 22:50 Go to last post
  3. Closed: help with CLA Adders in VHDL!!!!

    Started by cretafarm, 13th May 2008 01:05
    • Replies: 2
    • Views: 2,410
    13th May 2008, 17:09 Go to last post
  4. Closed: need a proposal for final year project

    Started by menz, 10th May 2008 12:50
    • Replies: 5
    • Views: 2,048
    13th May 2008, 08:09 Go to last post
  5. Closed: nios 2 external clock (and other FPGA as well)

    Started by childs, 13th May 2008 07:18
    • Replies: 0
    • Views: 697
    13th May 2008, 07:18 Go to last post
  6. Closed: Looking for info about memory arbiter

    Started by amburose, 10th May 2008 03:40
    • Replies: 1
    • Views: 1,180
    13th May 2008, 07:15 Go to last post
  7. Closed: How to detect turnaround cycle in PCI ?

    Started by gck, 13th May 2008 07:09
    • Replies: 0
    • Views: 1,108
    13th May 2008, 07:09 Go to last post
  8. Closed: How to implement checksum in VHDL?

    Started by Oana, 6th May 2008 14:53
    • Replies: 5
    • Views: 13,521
    13th May 2008, 06:57 Go to last post
  9. Closed: Floating Point Representation in Hardware

    Started by SyedSJ, 7th May 2008 20:38
    • Replies: 5
    • Views: 1,227
    12th May 2008, 17:03 Go to last post
  10. Closed: Info about creating VGA controller for XUPV2P board

    Started by BlackOps, 22nd February 2008 22:10
    • Replies: 5
    • Views: 1,870
    12th May 2008, 02:53 Go to last post
  11. Closed: My USB Portable Centralised license Flexlm Server

    Started by eltonjohn, 20th May 2003 19:24
    • Replies: 8
    • Views: 6,698
    11th May 2008, 12:45 Go to last post
  12. Closed: Quartus II Support for Modelsim 5.7g ?

    Started by SyedSJ, 11th May 2008 12:35
    • Replies: 0
    • Views: 1,530
    11th May 2008, 12:35 Go to last post
  13. Closed: Need help in designin multipliers

    Started by deepu_s_s, 30th April 2008 16:23
    • Replies: 1
    • Views: 745
    11th May 2008, 09:31 Go to last post
  14. Closed: Interfacing 3.3V FPGA logic with 5V amplifiers?

    Started by mcdpekala, 9th May 2008 22:34
    • Replies: 3
    • Views: 1,660
    11th May 2008, 03:26 Go to last post
  15. Closed: How to measure power, area and speed using Xilinx?

    Started by triump.ar, 9th May 2008 14:21
    • Replies: 4
    • Views: 3,383
    11th May 2008, 03:19 Go to last post
  16. Closed: NIOS 3.1 - how to install this core?

    Started by michland, 14th October 2003 08:37
    2 Pages
    1 2
    • Replies: 26
    • Views: 5,202
    11th May 2008, 03:19 Go to last post
  17. Closed: How to use the cores that are available in Xilinx ? (VHDL)

    Started by triump.ar, 10th May 2008 05:11
    • Replies: 1
    • Views: 870
    10th May 2008, 10:01 Go to last post
  18. Closed: Problem with one Verilog statement

    Started by firefoxPL, 8th May 2008 16:02
    • Replies: 5
    • Views: 864
    10th May 2008, 09:45 Go to last post
  19. Closed: DDR SDRAM Interface with Microblaze in EDK

    Started by pramodm, 17th September 2007 14:35
    • Replies: 6
    • Views: 3,621
    10th May 2008, 05:34 Go to last post
  20. Closed: architecture of ECU with fpga

    Started by tannazii, 9th May 2008 21:38
    • Replies: 0
    • Views: 841
    9th May 2008, 21:38 Go to last post
  21. Closed: Looking for general tutorials on Modelsim

    Started by husni132, 8th May 2008 04:57
    • Replies: 3
    • Views: 874
    9th May 2008, 07:02 Go to last post
  22. Closed: Interactive tutora needed

    Started by sidhuhere, 8th May 2008 18:31
    • Replies: 0
    • Views: 625
    8th May 2008, 18:31 Go to last post
  23. Closed: Xilinx ML300 evaluation board broken?

    Started by grubby23, 8th May 2008 16:31
    • Replies: 0
    • Views: 908
    8th May 2008, 16:31 Go to last post
  24. Closed: Please help me......................

    Started by deepu_s_s, 30th April 2008 06:28
    • Replies: 2
    • Views: 774
    8th May 2008, 11:51 Go to last post
  25. Closed: Display DDR SDRAM data on LEDs (XUPV2P)

    Started by BlackOps, 25th April 2008 07:45
    • Replies: 6
    • Views: 1,762
    8th May 2008, 07:19 Go to last post
  26. Closed: Digital Control System

    Started by 100ml, 30th April 2008 12:11
    • Replies: 5
    • Views: 1,177
    8th May 2008, 02:54 Go to last post
  27. Closed: VHDL : 'Integer' range and its use

    Started by GeekWizard, 7th May 2008 14:05
    • Replies: 2
    • Views: 2,828
    7th May 2008, 18:46 Go to last post
  28. Closed: Doubt again.................

    Started by deepu_s_s, 6th May 2008 12:55
    • Replies: 2
    • Views: 711
    7th May 2008, 18:18 Go to last post
  29. Closed: Usage of bit file of an FIR filter

    Started by salma ali bakr, 7th May 2008 13:06
    • Replies: 3
    • Views: 852
    7th May 2008, 14:13 Go to last post
  30. Closed: Unexpected TOKOUT error in VHDL code

    Started by loonym, 7th May 2008 12:10
    • Replies: 1
    • Views: 2,898
    7th May 2008, 12:24 Go to last post