1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    101,816
Page 3 of 736 FirstFirst 1 2 3 4 5 13 53 103 503 ... LastLast
Threads 61 to 90 of 22052

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Improve UART resource usage

    Started by promach, 10th December 2017 12:41
    • Replies: 1
    • Views: 494
    11th December 2017, 02:09 Go to last post
  2. [SOLVED] logic : give value in which require decimal number represent

    Started by tayyab786, 10th December 2017 14:05
    • Replies: 5
    • Views: 550
    10th December 2017, 22:10 Go to last post
  3. Circuit protection with VHDL code

    Started by manush30, 6th December 2017 08:40
    • Replies: 9
    • Views: 850
    10th December 2017, 10:54 Go to last post
  4. ADS (advanced Design System) Xilinx FPGA model kit

    Started by Enrocinu, 10th December 2017 00:00
    • Replies: 0
    • Views: 517
    10th December 2017, 00:00 Go to last post
    • Replies: 2
    • Views: 448
    9th December 2017, 20:11 Go to last post
    • Replies: 4
    • Views: 870
    9th December 2017, 16:34 Go to last post
  5. choosing high speed data storage element

    Started by amin5659, 7th December 2017 16:42
    • Replies: 10
    • Views: 855
    9th December 2017, 10:39 Go to last post
  6. [SOLVED] How to load program to A54SX16A-PQG208M FPGA?

    Started by Mithun_K_Das, 5th December 2017 12:17
    • Replies: 13
    • Views: 1,304
    9th December 2017, 05:34 Go to last post
    • Replies: 4
    • Views: 503
    8th December 2017, 22:19 Go to last post
  7. How to run two module in series using verilog

    Started by kapaa, 7th December 2017 03:21
    • Replies: 6
    • Views: 674
    7th December 2017, 22:44 Go to last post
  8. FPGA-Based Christmas project

    Started by bwarlord01, 6th December 2017 19:29
    • Replies: 3
    • Views: 552
    7th December 2017, 02:46 Go to last post
  9. What is Most Economic FPGA?

    Started by Zerox100, 5th December 2017 16:04
    • Replies: 2
    • Views: 477
    6th December 2017, 12:59 Go to last post
    • Replies: 0
    • Views: 324
    6th December 2017, 12:18 Go to last post
  10. Vendor specific macros for Igloo2

    Started by filip.amator, 5th December 2017 23:15
    • Replies: 2
    • Views: 639
    6th December 2017, 11:38 Go to last post
  11. ppg database regarding

    Started by josephine1234, 5th December 2017 12:00
    • Replies: 1
    • Views: 314
    5th December 2017, 12:13 Go to last post
  12. FPGA Ethernet interface

    Started by Vlad., 3rd December 2017 19:11
    • Replies: 3
    • Views: 1,231
    4th December 2017, 09:51 Go to last post
  13. Regarding Verilog codes

    Started by josephine1234, 1st December 2017 06:06
    • Replies: 5
    • Views: 919
    2nd December 2017, 13:07 Go to last post
  14. SPI communication (ALTERA board)

    Started by MiLaNa1995, 30th November 2017 14:19
    • Replies: 1
    • Views: 462
    2nd December 2017, 09:36 Go to last post
  15. Multiple users of a DDR interface

    Started by shaiko, 29th November 2017 21:08
    • Replies: 14
    • Views: 1,358
    2nd December 2017, 09:31 Go to last post
  16. Coding help in Verilog

    Started by josephine1234, 1st December 2017 06:04
    • Replies: 4
    • Views: 535
    1st December 2017, 13:18 Go to last post
  17. Implementation of output wrt clock in verilog

    Started by kapaa, 30th November 2017 08:24
    • Replies: 5
    • Views: 673
    1st December 2017, 07:01 Go to last post
  18. Interfacing a VGA port with a PLD

    Started by garvind25, 25th October 2017 07:16
    • Replies: 10
    • Views: 1,206
    1st December 2017, 06:10 Go to last post
  19. modelsim error during RTL simulation

    Started by hareeshP, 30th November 2017 15:07
    • Replies: 8
    • Views: 717
    30th November 2017, 19:33 Go to last post
  20. Data not appearing in waveform window

    Started by athuluri_mounika, 28th November 2017 13:08
    • Replies: 5
    • Views: 622
    30th November 2017, 19:22 Go to last post
  21. FPGA Vertex -6 ML605

    Started by tayyab786, 29th November 2017 03:04
    • Replies: 4
    • Views: 667
    30th November 2017, 17:06 Go to last post
  22. KCU105 configuration

    Started by wesleytaylor, 30th November 2017 12:14
    • Replies: 0
    • Views: 359
    30th November 2017, 12:14 Go to last post
  23. Programming an fpga board

    Started by moonshine8995, 29th November 2017 14:17
    • Replies: 2
    • Views: 463
    30th November 2017, 11:39 Go to last post
  24. using chipscope to check signals in a design

    Started by moonshine8995, 29th November 2017 09:00
    • Replies: 2
    • Views: 419
    29th November 2017, 19:47 Go to last post
  25. Microsemi FPGA, remove clock buffer

    Started by cocopa, 29th November 2017 12:12
    • Replies: 1
    • Views: 401
    29th November 2017, 19:41 Go to last post
    • Replies: 1
    • Views: 409
    29th November 2017, 17:49 Go to last post