1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    101,704
Page 2 of 736 FirstFirst 1 2 3 4 12 52 102 502 ... LastLast
Threads 31 to 60 of 22051

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED] Power Vs Area utilization in an FPGA

    Started by rafimiet, 28th December 2017 06:26
    • Replies: 8
    • Views: 587
    30th December 2017, 15:23 Go to last post
  2. Moved: Comparison of area utilization among various FPGAs

    Started by rafimiet, 30th December 2017 11:44
    •  
    •  
  3. SignalTap waiting for clock

    Started by hareeshP, 28th December 2017 10:33
    • Replies: 5
    • Views: 419
    29th December 2017, 10:39 Go to last post
  4. Need code for reference

    Started by Merlin10, 28th December 2017 19:10
    • Replies: 0
    • Views: 315
    28th December 2017, 19:10 Go to last post
  5. Direct memory access through VDMA and DMA

    Started by DilshanSampath, 28th December 2017 16:32
    • Replies: 0
    • Views: 307
    28th December 2017, 16:32 Go to last post
  6. Altera Stratix 10 Hyper-Registers

    Started by Wiljan, 9th December 2017 14:24
    • Replies: 9
    • Views: 1,059
    26th December 2017, 12:12 Go to last post
    • Replies: 1
    • Views: 288
    26th December 2017, 11:17 Go to last post
  7. [SOLVED] Simulation time in simulation tools like ISIM/model sim

    Started by mjuneja, 5th December 2017 08:25
    • Replies: 6
    • Views: 958
    26th December 2017, 06:59 Go to last post
  8. [SOLVED] Low speed on hps to fpga bridge

    Started by dipin, 23rd December 2017 15:57
    • Replies: 2
    • Views: 481
    24th December 2017, 14:09 Go to last post
    • Replies: 0
    • Views: 313
    23rd December 2017, 11:14 Go to last post
    • Replies: 4
    • Views: 482
    23rd December 2017, 07:57 Go to last post
  9. Vivado debuging and keep attribute!

    Started by Port Map, 20th December 2017 13:18
    • Replies: 2
    • Views: 436
    20th December 2017, 15:24 Go to last post
  10. Changing IP parameters in Vivado using HDL generics

    Started by shaiko, 13th December 2017 15:30
    • Replies: 13
    • Views: 932
    19th December 2017, 20:27 Go to last post
  11. help regarding fpga implemetation

    Started by kumar1988, 2nd September 2013 18:01
    • Replies: 16
    • Views: 1,178
    19th December 2017, 15:33 Go to last post
  12. Compile package into "ieee_proposed"

    Started by Hugo17, 19th December 2017 13:20
    • Replies: 1
    • Views: 352
    19th December 2017, 13:56 Go to last post
  13. Overcoming the 8:1 width conversion problem

    Started by shaiko, 17th December 2017 19:14
    • Replies: 5
    • Views: 591
    19th December 2017, 13:25 Go to last post
  14. Vivado HLS Experience

    Started by MarkPh, 1st December 2017 15:58
    • Replies: 6
    • Views: 1,135
    19th December 2017, 11:21 Go to last post
  15. AXI 4 Stream Data Width Converter

    Started by Vlad., 13th December 2017 08:22
    • Replies: 11
    • Views: 901
    18th December 2017, 14:49 Go to last post
    • Replies: 2
    • Views: 417
    18th December 2017, 04:39 Go to last post
  16. Scope of STA in FPGAs

    Started by hareesh007, 16th December 2017 13:26
    • Replies: 3
    • Views: 481
    18th December 2017, 03:49 Go to last post
    • Replies: 1
    • Views: 462
    18th December 2017, 02:40 Go to last post
  17. FPGA Based Car Game (Christmas Themed)

    Started by bwarlord01, 16th December 2017 15:26
    • Replies: 1
    • Views: 490
    16th December 2017, 19:46 Go to last post
  18. Vivado - math.real support

    Started by shaiko, 14th December 2017 12:37
    • Replies: 7
    • Views: 578
    15th December 2017, 13:12 Go to last post
  19. SSD performance gain

    Started by shaiko, 12th December 2017 17:27
    • Replies: 7
    • Views: 695
    14th December 2017, 09:45 Go to last post
  20. OpenCL GPU vs FPGA implementation

    Started by shaiko, 13th December 2017 01:23
    • Replies: 1
    • Views: 465
    13th December 2017, 16:35 Go to last post
  21. Generate desired random number in range in verilog

    Started by tayyab786, 27th November 2017 20:14
    2 Pages
    1 2
    • Replies: 20
    • Views: 2,442
    11th December 2017, 23:48 Go to last post
  22. FPGA USB Data software

    Started by expertengr, 9th December 2017 12:10
    • Replies: 5
    • Views: 755
    11th December 2017, 19:52 Go to last post
  23. [SOLVED] Round robin arbiter with ring counter.

    Started by ppko1233, 10th December 2017 14:26
    • Replies: 1
    • Views: 469
    11th December 2017, 16:48 Go to last post
  24. Improve UART resource usage

    Started by promach, 10th December 2017 12:41
    • Replies: 1
    • Views: 494
    11th December 2017, 02:09 Go to last post